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PDF KS8721CL Data sheet ( Hoja de datos )
| Número de pieza | KS8721CL | |
| Descripción | 3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KS8721CL
KS8721CL
Micrel, Inc.
3.3V Single Power Supply 10/100BASE-TX/FX MII Physical Layer Transceiver
Rev. 1.2
General Description
The KS8721CL is a 10BASE-T, 100BASE-TX, and 100BASE-
FX physical layer transceiver providing MII/RMII interfaces to
MACs and switches. Using a unique mixed-signal design that
extends signaling distance while reducing power consump-
tion, the KS8721CL represents Micrel’s fourth generation
single-port Fast Ethernet PHY.
The KS8721CL contains 10BASE-T physical medium attach-
ment (PMA), physical medium dependent (PMD), and physi-
cal coding sub-layer (PCS) functions. It also has on-chip
10BASE-T output filtering. This eliminates the need for
external filters and allows a single set of line magnetics to be
used to meet requirements for both 100BASE-TX and
10BASE-T.
The KS8721CL automatically configures itself for 100Mbps
or 10Mbps and full- or half-duplex operation, using an on-chip
auto-negotiation algorithm. It is the ideal physical layer
transceiver for 100BASE-TX/10BASE-T applications.
Features
• Single chip 100BASE-TX/100BASE-FX/10BASE-T
physical layer solution
• 2.5V CMOS design; 2.5/3.3V tolerance on I/O
• 3.3V single power supply with built-in voltage regulator;
Power consumption <340mW (including output driver
current)
• Fully compliant to IEEE 802.3u standard
• Supports MII and Reduced MII (RMII)
• Supports 10BASE-T, 100BASE-TX, and 100BASE-FX
with far-end-fault (FEF) detection
• Supports power-down and power-saving modes
• Configurable through MII serial management ports or via
external control pins
• Supports auto-negotiation and manual selection for
10/100Mbps speed and full-/half-duplex modes
• On-chip, built-in, analog front-end filtering for both
100BASE-TX and 10BASE-T
• Available in Lead-free and Industrial Temperature
packages.
Functional Diagram
TX+
Transmitter
TX-
10/100
Pulse
Shaper
Adaptive EQ
RX+ Base Line
Wander Correction
RX- MLT3 Decoder
NRZI/NRZ
www.DataSheet4U.com
XI
XO
10BaseT
Receiver
PLL
NRZ/NRZI
MLT3 Encoder
Clock
Recovery
Auto
Negotiation
Power
Down or
Saving
PWRDWN
4B/5B Encoder
Scrambler
Parallel/Serial
Parallel/Serial
Manchester Encoder
4B/5B Decoder
Descrambler
Serial/Parallel
Manchester Decoder
Serial/Parallel
MII/RMII
Registers
and
Controller
Interface
TXD3
TXD2
TXD1
TXD0
TXER
TXC
TXEN
CRS
COL
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RXER
RXDV
RXC
LED
Driver
LINK
ACTIVITY
FDX
SPD
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2005
1 M9999-041405
1 page  
KS8721CL
Micrel, Inc.
Register Map (continued)
Register 15h: RXER Counter ...................................................................................................................................... 21
Register 1bh: Interrupt Control/Status Register .......................................................................................................... 21
Register 1fh: 100BASE-TX PHY Controller ................................................................................................................ 21
Absolute Maximum Ratings ........................................................................................................................................ 23
Operating Ratings ........................................................................................................................................................ 23
Electrical Characteristics ............................................................................................................................................ 23
Timing Diagrams .......................................................................................................................................................... 25
Selection of Isolation Transformer ............................................................................................................................ 31
Selection of Reference Crystal ................................................................................................................................... 31
Package Information ................................................................................................................................................... 32
www.DataSheet4U.com
April 2005
5
M9999-041405
5 Page 
KS8721CL
Micrel, Inc.
Introduction
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, NRZ-to-NRZI conversion, and MLT-3 encoding and
transmission. The circuitry starts with a parallel to serial conversion that converts the 25MHz, 4-bit nibbles into a 125MHz serial
bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted from
NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49kΩ resistor
for the 1:1 transformer ratio. Its typical rise/fall time of 4ns complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-TX
driver.
100BASE-TX Receive
The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to-NRZI conversion, data and clock
recovery, NRZI-to-NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equalization filter to
compensate for inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are
a function of the length of the cable, the equalizer has to adjust its characteristic to optimize performance. In this design, the
variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable
characteristics. It then tunes itself for optimization. This is an ongoing process and can self-adjust for environmental changes
such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effects of base line wander and improve dynamic range. The differential data conversion circuit converts
the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A
synchronized 25MHz RXC is generated so that the 4B nibbles are clocked out at the negative edge of RCK25 and is valid for
the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference
clock and both TXC and RXC clocks continue to run.
PLL Clock Synthesizer
The KS8721CL generates 125MHz, 25MHz, and 20MHz clocks for system timing. An internal crystal oscillator circuit provides
the reference clock for the synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic interference
(EMI) and baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding and transmission begins. The KS8721CL continues to encode and
transmit data as long as TXEN remains high. The data transmission ends when TXEN goes low. The last transition occurs at
the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is incorporated
into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-
emphasized into outputs with a typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when
driven by an all-ones, Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a
PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A
squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noise at the RX+ or
RX- input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal
and the KS8721CL decodes a data frame. This activates the carrier sense (CRS) and RXDV signals and makes the receive
data (RXD) available. The receive clock is maintained active during idle periods in between data reception.
wwwS.DQaEtaSahneedt4JUa.cbomber Function (10BASE-T only)
In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a test of
the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL goes high if
TXEN is high for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BASE-T transmitter is re-
enabled and COL goes low.
Auto-Negotiation
The KS8721CL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It automatically
chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner whenever
April 2005
11 M9999-041405
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet KS8721CL.PDF ] | |
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