DataSheet.es    


PDF L29C525JC15 Data sheet ( Hoja de datos )

Número de pieza L29C525JC15
Descripción Dual Pipeline Register
Fabricantes LOGIC Devices Incorporated 
Logotipo LOGIC Devices Incorporated Logotipo



Hay una vista previa y un enlace de descarga de L29C525JC15 (archivo pdf) en la parte inferior de esta página.


Total 6 Páginas

No Preview Available ! L29C525JC15 Hoja de datos, Descripción, Manual

DEVICES INCORPORATED
DEVICES INCORPORATED
L29C525
Dual PLip2el9inCe R5eg2is5ter
Dual Pipeline Register
FEATURES
DESCRIPTION
u Dual 8-Deep Pipeline Register
u Configurable to Single 16-Deep
u Low Power CMOS Technology
u Replaces AMD Am29525
u Load, Shift, and Hold Instructions
u Separate Data In and Data Out Pins
u Three-State Outputs
u Package Styles Available:
• 28-pin Plastic DIP
• 28-pin Plastic LCC, J-Lead
The L29C525 is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration imple-
mented is determined by the instruc-
tion code (I1-0) as shown in Table 2.
The I1-0 instruction code controls the
internal routing of data and loading of
each register. For instruction I1-0 = 00
(Push A and B), data applied at the
D7-0 inputs is latched into register A0
on the rising edge of CLK. The
contents of A0 simultaneously move
to register A1, A1 moves to A2, and so
on. The contents of register A7 are
wrapped back to register B0. The
registers on the B side are similarly
shifted, with the contents of register
B7 lost.
Instruction I1-0 = 01 (Push B) acts
similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register B0, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction I1-0 = 10 (Push
A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.
Instruction I1-0 = 11 (Hold) causes no
internal data movement. It is equiva-
lent to preventing the application of a
clock edge to any internal register.
The contents of any of the registers is
selectable at the output through the
use of the S3-0 control inputs. The
independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S3-0 controls
is given in Table 3.
L29C525 BLOCK DIAGRAM
D7-0
I1-0
CLK
8
2
A0
A1
A2
A3
A4
A5
A6
A7
Y7-0
B0 8
B1
OE
B2
B3
B4
B5
B6
B7
S3-0
4
Pipeline Registers
1 03/23/2000–LDS.29C525-G

1 page




L29C525JC15 pdf
DEVICES INCORPORATED
L29C525
Dual Pipeline Register
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. Thisdeviceprovideshardclampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
NCV2 F
4
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of IOH and IOL respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 µF ceramic capacitor should be
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
CL
IOL
VTH
IOH
FIGURE B. THRESHOLD LEVELS
tENA
tDIS
OE 1.5 V
1.5 V
Z0
1.5 V
VOL* 0.2 V
3.5V Vth
0Z
Z1
1.5 V
VOH* 0.2 V
1Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
Pipeline Registers
5 03/32/2000–LDS.29C525-G

5 Page










PáginasTotal 6 Páginas
PDF Descargar[ Datasheet L29C525JC15.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
L29C525JC15Dual Pipeline RegisterLOGIC Devices Incorporated
LOGIC Devices Incorporated

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar