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PDF PA7140 Data sheet ( Hoja de datos )
| Número de pieza | PA7140 | |
| Descripción | Programmable Electrically Erasable Logic Array | |
| Fabricantes | Integrated Circuit Technology | |
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Commercial/
Industrial
PA7140 PEELTM Array
Features
Programmable Electrically Erasable Logic Array
s Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
s CMOS Electrically Erasable Technology
- Reprogrammable in 40-pin DIP,
- Up to 72 logic cell output functions
44-pin PLCC, and TQFP packages
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
s Flexible Logic Cell
- Up to 3 output functions per logic cell
s High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX)
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
- Industrial grade available for 4.5 to 5.5V Vcc and -40
clock polarity and output enables
to +85 °C temperatures Ideal for Combinatorial,
- Sum-of-products logic for output enables
Synchronous and Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
s Development and Programmer Support
- ICT PLACE Development Software
-Fitters for ABEL, CUPL and other software
-Programming support for by ICT PDS-3 and popular
General Description
third-party programmers
The PA7140 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today’s pro-
grammable logic designs. The PA7140 offers a versatile
logic array architecture with 24 I/O pins, 14 input pins and
60 registers/latches (24 buried logic cells, 12 input regis-
ters/latches, 24 buried I/O registers/latches). Its logic array
implements 100 sum-of-products logic functions divided
into two groups each serving 12 logic cells. Each group
shares half (60) of the 120 product-terms available for logic
cells.
The PA7140’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7140 suitable for a variety of combinatorial, synchro-
nous and asynchronous logic applications. The PA7140
supports speeds as fast as 13ns/20ns (tpdi/tpdx) and
66.6MHz (fMAX) at moderate power consumption 140mA
(100mA typical). Packaging includes 40-pin DIP and 44-pin
PLCC (see Figure 1). Development and programming sup-
port for the PA7140 is provided by ICT and popular third-
party development tool manufacturers.
Figure 1: Pin Configuration
Figure 2. Block Diagram
www.DataSheet4U.com
TQFP
44 43 42 41 40 39 38 37 36 35 34
1 Pin 1
33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
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1 page  
Sequential Timing - Waveforms and Block Diagram
PA7140
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for
periods less than 20ns.
2. Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced
at 10% and 90% levels.
3. I/O pins are 0V or VCC.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
ww7. wtO.EDisatmaeSahseuerte4dUfr.coomminput transition to VREF ±0.1V (See test loads at
end of Section 6 for VREF value). tOD is measured from input transition
to VOH -0.1V or VOL +0.1V.
8. DIP: “System-clock” refers to pin 1/21 high speed clocks. PLCC: “Sys-
tem-clock” refers to pin 2/24 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of this Data Book.
13. “Async. clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “IOC” term indicates that the timing parameter is
applied to the IOC register. The “LCC/IOC” term indicates that the tim-
ing parameter is applied to both the LCC and IOC registers. The “LCC/
IOC/INC” term indicates that the timing parameter is applied to the
LCC, IOC and INC registers.
15. This refers to the Sum-D gate routed to the IOC register for an addi-
tional buried register
16. The term “Input” without any reference to another term refers to an
(external) input pin.
17. The parameter tSPI indicates that the PCLK signal to the IOC register is
always slower than the data from the pin or input by the absolute value
of (tSK -tPK -tIA). This means that no set-up time for the data from the
pin or input is required, i.e. the external data and clock can be sent to
the device simultaneously. Additionally, the data from the pin must
remain stable for tHPI time, i.e. to wait for the PCLK signal to arrive at
the IOC register.
18. Typical (typ) ICC is measured at TA =25° C, Freq = 25MHz, VCC =5V.
5 of 6
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