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PDF KA100O015E-BJTT Data sheet ( Hoja de datos )
| Número de pieza | KA100O015E-BJTT | |
| Descripción | 2CKE DDP Mobile DDR SDRAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KA100O015E-BJTT (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Rev. 1.0, Jul. 2010
KA100O015E-BJTT
MCP Specification
4Gb (256M x16) NAND Flash
+ 4Gb (64M x32 + 64M x32) 2/CS,2CKE DDP Mobile DDR SDRAM
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
www.DataSAhlel berta4nUd.cnoammes, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
-1-
1 page  
KA100O015E-BJTT
datasheet
3. PIN CONFIGURATION
Rev. 1.0
MCP Memory
- 1 2 3 4 5 6 7 8 9 10
A - DNU -
-
-
-
-
-
DNU
DNU
B
NC
CKE2d
/REn
CLEn
VCCn
/CEn
/WEn
VDDd
VSSd
NC
C
VSSd
A4d
/WPn
ALEn
VSSn
R/Bn
DQ31d
DQ30d
VDDQd
VSSQd
D
VDDd
A5d
A7d
A9d
DQ25d
DQ27d
DQ29d
DQ28d
VSSQd
VDDQd
E
A6d
A8d
CKE1d
DQ18d
DQS3d
DQ22d
DM3d
DQ26d
VDDQd
VSSQd
F
A12d
A11d
/CS2d
DQ17d
DQ19d
DQ24d
DQ23d
DM2d
VSSQd
VDDQd
G
NC
/RASd
DQ15d
DQ16d
DQS1d
DM1d
DQ9d
CKd
VDDQd
VSSQd
H
VDDd
/CASd
DQ20d
DQ21d
DQ13d
DQ12d
DQS2d
/CKd
VSSd
VDDd
J
VSSd
/CS1d
BA0d
DQ14d
DQ11d
DQ10d
DQS0d
DM0d
VSSQd
VDDQd
K
/WEd
BA1d
A10d
A0d
DQ7d
DQ8d
DQ6d
DQ4d
VDDQd
VSSQd
L
A1d
A2d
A3d
DQ0d
DQ1d
DQ2d
DQ3d
DQ5d
VDDQd
VSSQd
M
VDDd
VSSd
A13d
NC
IO3n
IO5n
IO14n
IO7n
VSSQd
VDDQd
N
IO0n
IO1n
IO2n
IO10n
VCCn
IO6n
IO13n
IO15n
VDDQd
VSSQd
P
NC
IO8n
IO9n
IO11n
IO12n
VSSn
IO4n
VDDd
VSSd
NC
R
DNU
DNU
-
-
-
-
-
-
DNU
DNU
137 FBGA: Top View (Ball Down)
NAND
Mobile DRAM
Power
Ground
NC/DNU
www.DataSheet4U.com
-5-
5 Page 
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
VCC
VSS
A13 - A30*
X-Buffers
Latches
& Decoders
A0 - A12
Y-Buffers
Latches
& Decoders
4,096M + 128M Bit for 4Gb
8,192M + 256M Bit for 8Gb DDP
NAND Flash
ARRAY
Data Register & S/A
Y-Gating
Command
CE
RE
WE
Command
Register
Control Logic
& High Voltage
Generator
I/O Buffers & Latches
Global Buffers
Output
Driver
CLE ALE WP
[Figure 1] Functional Block Diagram
VCC
VSS
I/0 0
I/0 7
1 Block = 64 Pages
(256K + 8K) Byte
2,048 blocks for 4Gb
4,096 blocks for 8Gb DDP
4K Bytes
128 Bytes
1 Page = (4K + 128)Bytes
1 Block = (4K + 128)Byte x 64 Pages
= (256K + 8K) Bytes
1 Device = (4K+128)B x 64Pages x 2,048 Blocks
= 4,224 Mbits for 4Gb
8 bit 1 Device = (4K+128)B x 64Pages x 4,096 Blocks
= 8,448 Mbits for 8Gb DDP
Page Register
4K Bytes
I/O 0 ~ I/O 7
128 Bytes
[Figure 2] Array Organization
[Table 1] Array address (x8)
I/O 0
I/O 1
1st Cycle
A0
A1
2nd Cycle
A8
A9
3rd Cycle
A13
A14
4th Cycle
A21
A22
5th Cycle
A29
*A30
I/O 2
A2
A10
A15
A23
*L
I/O 3
A3
A11
A16
A24
*L
I/O 4
A4
A12
A17
A25
*L
wNOwTEw:.DataSheet4U.com
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* A30 is Row address for 8G DDP.
In case of 4G Mono, A30 must be set to "Low"
I/O 5
A5
*L
A18
A26
*L
I/O 6
A6
*L
A19
A27
*L
I/O 7
A7
*L
A20
A28
*L
Address
Column Address
Column Address
Row Address
Row Address
Row Address
- 11 -
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