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PDF K8A57ETC Data sheet ( Hoja de datos )

Número de pieza K8A57ETC
Descripción 256Mb C-die NOR FLASH
Fabricantes Samsung semiconductor 
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Rev. 1.0, Nov. 2010
K8A56(57)ET(B)(Z)C
256Mb C-die NOR FLASH
16M x16, Synch Burst
Multi Bank SLC NOR Flash
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
www.DataSAhlel berta4nUd.cnoammes, trademarks and registered trademarks belong to their respective owners.
2009 Samsung Electronics Co., Ltd. All rights reserved.
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K8A57ETC pdf
K8A56(57)15ET(B)(Z)C
datasheet
NOR
FLASH
Rev.
MEMORY
1.0
256M Bit (16M x16) Synch Burst , Multi Bank SLC NOR Flash Memory
1.0 FEATURES
2.0 GENERAL DESCRIPTION
Single Voltage, 1.7V to 1.95V for Read and Write operations
The K8A(56/57)15E featuring single 1.8V power supply is a 256Mbit Burst
Organization
Multi Bank Flash Memory organized as 16Mx16. The memory architecture
- 16,777,216 x 16 bit ( Word Mode Only)
of the device is designed to divide its memory arrays into 256 blocks(Uni-
Read While Program/Erase Operation
form block part)/259 blocks(Boot block part) with independent hardware
Multiple Bank Architecture
protection. This block architecture provides highly flexible erase and pro-
- 16 Banks (16Mb Partition)
gram capability. The K8A(56/57)15E NOR Flash consists of sixteen banks.
OTP Block : Extra 512-Word block
This device is capable of reading data from one bank while programming or
Read Access Time (@ CL=30pF)
erasing in the other bank.
- Asynchronous Random Access Time : 100ns
Regarding read access time, the K8A5615E provides an 11ns burst access
- Synchronous Random Access Time :95ns
time and an 95ns initial access time at 66MHz. At 83MHz, the K8A5615E
- Burst Access Time :
provides an 9ns burst access time and an 95ns initial access time. At
11ns(66Mhz) / 9ns(83Mhz) / 7ns (108MHz) / 6ns (133MHz)
108MHz, the K8A5715E provides an 7ns burst access time and an 95ns ini-
Page Mode Operation
tial access time. At 133MHz, the K8A5715E provides an 6ns burst access
16Words Page access allows fast asynchronous read
time and an 95ns initial access time.
Page Read Access Time :
The device performs a program operation in units of 16 bits (Word) and
18ns(66/83Mhz) / 15ns(108/133Mhz)
erases in units of a block. Single or multiple blocks can be erased. The
Burst Length :
block erase operation is completed within typically 0.6sec. The device
- Continuous Linear Burst
requires 25mA as program/erase current in the extended temperature
- Linear Burst : 8-word & 16-word with Wrap
ranges.
Block Architecture
The K8A(56/57)15E NOR Flash Memory is created by using Samsung's
- Uniform block part (K8A(56/57)15EZC) : Two hundred fifty-six
advanced CMOS process technology.
64Kword blocks
- Boot block part (K8A(56/57)15ET(B)C) : Four 16Kword blocks and two
3.0 PIN DESCRIPTIONhundred fifty-five 64Kword blocks (Bank 0 contains four 16 Kword blocks
and fifteen 64Kword blocks, Bank 1 ~ Bank 15 contain two hundred forty
64Kword blocks)
Pin Name
Pin Function
Reduce program time using the VPP
A0 - A23
Address Inputs
Support 32-word Buffer Program
Power Consumption (Typical value, CL=30pF)
- Synchronous Read Current : 35mA
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
- Standby Mode/Auto Sleep Mode : 30uA
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=VIL
(Boot block part : K8A(56/57)15ET(B)C)
- Last one block (BA255) is protected by WP=VIL
(Uniform block part : K8A(56/57)15EZC)
- All blocks are protected by VPP=VIL
Handshaking Feature
- Provides host system with minimum latency by monitoring RDY
Erase Suspend/Resume
Program Suspend/Resume
Unlock Bypass Program/Erase
Hardware Reset (RESET)
Deep Power Down Mode
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
Endurance
- 100K Program/Erase Cycles Minimum
Extended Temperature : -25°C ~ 85°C
Support Common Flash Memory Interface
Output Driver Control by Configuration Register
Low Vcc Write Inhibit
wwPawck.Dagaeta:SThBeDet4U.com
DQ0 - DQ15
CE
OE
RESET
VPP
WE
WP
CLK
RDY
AVD
DPD
Vcc
VSS
Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Deep Power Down
Power Supply
Ground
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K8A57ETC arduino
K8A56(57)15ET(B)(Z)C
datasheet
NOR
FLASH
Rev.
MEMORY
1.0
7.0 PRODUCT INTRODUCTION
The K8A(56/57)15E is 256Mbit (268,435,456 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within
the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs.
The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device
adapts a block memory architecture that divides its memory array into 256 blocks (64-Kword x 256 blocks, Uniform block part) / 259 blocks (16-Kword x 4
+ 64-Kword x 255, Boot block part). Programming is done in units of 16 bits (Word). Programming is done in units of 16 bits (Word). All bits of data in one
or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the pro-
grammed data, 256 / 259 memory blocks can be hardware protected. Regarding read access time, the K8A5615E provides 11ns burst access time and
95ns initial access time at 66MHz. At the K8A5615E provides 9ns burst access time and 95ns initial access time at 83MHz. At the K8A5715E provides
7ns burst access time and 95ns initial access time at 108MHz. At 133MHz, the K8A5715E provides 6ns burst access time and 95ns initial access time.
The command set of K8A(56/57)15E is compatible with standard Flash devices. The device uses Chip Enable (CE), Write Enable (WE), Output Enable
(OE) to control asynchronous read and write operation. For burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device oper-
ations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command
registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry.
Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8A(56/57)15E is implemented
with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase
command sequences. The Internal Program Routine automatically programs and verifies data at specified addresses. The Internal Erase Routine auto-
matically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8A(56/57)15E has means to indicate the
status of completion of program/erase operations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have
been completed, the device automatically resets itself to the read mode. The device requires only 35mA as burst and asynchronous mode read current
and 25 mA for program/erase operations.
[Table 7] Device Bus Operations
Operation
Asynchronous Read Operation
Write
Standby
Hardware Reset
Load Initial Burst Address
Burst Read Operation
Terminate Burst Read Cycle
Terminate Burst Read Cycle via RESET
Terminate Current Burst Read Cycle and Start
New Burst Read Cycle
NOTE : L=VIL (Low), H=VIH (High), X=Don’t Care.
CE OE WE A0-23
L L H Add In
DQ0-15
I/O
RESET
H
CLK
L
AVD
L
LH
Add In
I/O
HL X
HXX
X
High-Z
H
X
X
XXX
X
High-Z
L
X
X
L H H Add In
X
H
L LH
X
Burst
DOUT
H
H
HXX
X
High-Z
H
X
X
XXX
X
High-Z
L
X
X
L H H Add In
I/O
H
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