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PDF K7S3236U4C Data sheet ( Hoja de datos )

Número de pieza K7S3236U4C
Descripción 1Mx36 & 2Mx18 QDR II b4 SRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K7S3236U4C
K7S3218U4C
1Mx36 & 2Mx18 QDRTM II+ b4 SRAM
36Mb QDRII+ SRAM Specification
165 FBGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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- 1 - Rev. 1.0 August 2008

1 page




K7S3236U4C pdf
K7S3236U4C
K7S3218U4C
1Mx36 & 2Mx18 QDRTM II+ b4 SRAM
PIN CONFIGURATIONS(TOP VIEW) K7S3218T4C (2Mx18)
1 2 3 4 5 6 7 8 9 10 11
A CQ NC/SA* SA W BW1 K NC R SA NC/SA* CQ
B NC Q9 D9 SA NC
K
BW0
SA
NC
NC
Q8
C NC NC D10 VSS SA NC SA VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
NC
Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS SA SA SA VSS NC NC D1
P NC NC Q17 SA SA QVLD SA SA NC D0 Q0
R TDO TCK
SA
SA
SA
NC
SA
SA
SA TMS TDI
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 10A for 72Mb and 2A for 144Mb.
2. BW0 controls write to D0:D8 and BW1 controls write to D9:D17.
PIN NAME
SYMBOL
K, K
QVLD
CQ, CQ
Doff
SA
D0-17
PIN NUMBERS
6B, 6A
6P
11A, 1A
1H
3A,9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D
3F,2G,3J,3L,3M,2N
DESCRIPTION
Input Clock
Q Valid output
Output Echo Clock
DLL Disable
Address Inputs
Data Inputs
NOTE
Q0-17
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E
2F,3G,3K,2L,3N,3P
Data Outputs
W 4A Write Control Pin,active when low
R 8A Read Control Pin,active when low
BW0, BW1
7B, 5A
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ 11H Output Driver Impedance Control Input 1
VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply (1.8 V)
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply (1.5V)
VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI 11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
2A,7A,10A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,1F
NC 9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M
No Connect
2
2M,9M,1N,9N,10N,1P,2P,9P,6R
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1. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
2. Not connected to chip pad internally.
3. K, K can not be set to VREF voltage.
- 5 - Rev. 1.0 August 2008

5 Page





K7S3236U4C arduino
K7S3236U4C
K7S3218U4C
1Mx36 & 2Mx18 QDRTM II+ b4 SRAM
DC ELECTRICAL CHARACTERISTICS (VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX UNIT NOTES
Input Leakage Current
IIL VDD=Max ; VIN=VSS to VDDQ
-2 +2 µA
Output Leakage Current
IOL Output Disabled,
-2 +2 µA
Operating Current (x36): QDR
ICC
VDD=Max , IOUT=0mA
Cycle Time tKHKH Min
-45 -
-40 -
-33 -
1050
950
850
mA 1,4
Operating Current (x18): QDR
ICC
VDD=Max , IOUT=0mA
Cycle Time tKHKH Min
-45 -
-40 -
-33 -
900
850 mA 1,4
750
Standby Current(NOP): QDR
-45
Device deselected, IOUT=0mA, f=Max,
ISB1 All Inputs0.2V or VDD-0.2V
-40
-33
-
-
-
400
350 mA 1,5
300
Output High Voltage
VOH1
VDDQ/2-0.12 VDDQ/2+0.12 V
2,6
Output Low Voltage
VOL1
VDDQ/2-0.12 VDDQ/2+0.12 V
2,6
Output High Voltage
VOH2 IOH=-1.0mA
VDDQ-0.2
VDDQ
V3
Output Low Voltage
VOL2 IOL=1.0mA
VSS 0.2 V 3
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ 350. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ 350.
3. Minimum Impedance Mode when ZQ pin is connected to VDD.
4. Operating current is calculated with 50% read cycles and 50% write cycles.
5. Standby Current is only after all pending read and write burst operations are completed.
6. Programmable Impedance Mode.
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- 11 - Rev. 1.0 August 2008

11 Page







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