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PDF K6R4004C1C-E Data sheet ( Hoja de datos )
| Número de pieza | K6R4004C1C-E | |
| Descripción | 1Mx4 Bit High Speed Static RAM | |
| Fabricantes | Samsung semiconductor | |
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PRELIMINARY
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E CMOS SRAM
Document Title
1Mx4 Bit High Speed Static RAM(5V Operating).
Operated at Extended and Industrial Temperature Ranges.
Revision History
RevNo.
Rev. 0.0
Rev. 1.0
Rev. 2.0
History
Initial release with Preliminary.
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics
1.3 Changed ISB1 to 20mA
2.1 Relax D.C parameters.
Item
12ns
ICC 15ns
20ns
Previous
160mA
155mA
150mA
Current
190mA
185mA
180mA
Draft Data
Feb. 12. 1999
Mar. 29. 1999
Remark
Preliminary
Preliminary
Aug. 19. 1999 Preliminary
Rev. 3.0
2.2 Relax Absolute Maximum Rating.
Item
Voltage on Any Pin Relative to Vss
Previous
-0.5 to 7.0
Current
-0.5 to Vcc+0.5
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
10ns
12ns
15ns
20ns
ICC
-
190mA
185mA
180mA
Previous
Isb
70mA
Isb1
20mA
ICC
160mA
150mA
140mA
130mA
Current
Isb
60mA
Isb1
10mA
Mar. 27. 2000 Final
3.3 Added Extended temperature range
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The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 3.0
March 2000
1 page  
PRELIMINARY
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E CMOS SRAM
WRITE CYCLE*
Parameter
Symbol
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
K6R4004C1C-10
Min Max
10 -
7-
0-
7-
7-
10 -
0-
05
5-
0-
3-
K6R4004C1C-12
Min Max
12 -
8-
0-
8-
8-
12 -
0-
06
6-
0-
3-
* The above parameters are also guaranteed at extended and industrial temperature range.
K6R4004C1C-15
Min Max
15 -
10 -
0-
10 -
10 -
15 -
0-
07
7-
0-
3-
K6R4004C1C-20
Min Max
20 -
12 -
0-
12 -
12 -
20 -
0-
09
9-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
Current
ICC
ISB
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tRC
tHZ(3,4,5)
Valid Data
tOHZ
tOH
tPD
50%
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NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
-5-
Rev 3.0
March 2000
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet K6R4004C1C-E.PDF ] | |
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