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PDF K4H510838F Data sheet ( Hoja de datos )

Número de pieza K4H510838F
Descripción 512Mb F-die DDR SDRAM Specification
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K4H510438F
K4H510838F
K4H511638F
DDR SDRAM
512Mb F-die DDR SDRAM Specification
66 TSOP-II
with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
www.Data1S.hFeoert4uUp.dcaotmes or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.1 November 2008

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K4H510838F pdf
K4H510438F
K4H510838F
K4H511638F
4.0 Pin Description
32Mb x 16
64Mb x 8
128Mb x 4
DDR SDRAM
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 66Pin TSOPII 57
11 (400mil x 875mil) 56
12 (0.65mm Pin Pitch) 55
13 54
14
15
Bank Address
BA0~BA1
16
53
52
51
17
18
19
Auto Precharge
A10
50
49
48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
512Mb TSOP-II Package Pinout
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
www.DataSheet4U.com
Organization
128Mx4
64Mx8
32Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0~A9, A11, A12
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
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Rev. 1.1 November 2008

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K4H510838F arduino
K4H510438F
K4H510838F
K4H511638F
DDR SDRAM
12.0 DDR SDRAM IDD Spec Items & Test Conditions
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Precharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
Vin = Vref for DQ,DQS and DM.
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min), tCK=7.5ns for DDR266,
6ns for DDR333, 5ns for DDR400; Address and other control inputs changing once per clock cycle; Vin = Vref for
DQ,DQS and DM
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; Address and other control inputs sta-
ble at >= VIH(min) or =<VIL(max); VIN = VREF for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max) ,tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400;
DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock
cycle
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=2.5 at tCK=7.5ns for DDR266, tCK=6ns for DDR333, CL=3 at tCK=5ns
for DDR400; 50% of data changing on every transfer; lout = 0 m A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=2.5 at tCK=7.5ns for DDR266, 6ns
for DDR333, 5ns for DDR400; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing
at every burst
Auto refresh current; tRC = tRFC(min) which is 16*tCK for DDR266 at tCK=7.5ns; 20*tCK for DDR333 at
tCK=6ns, 24*tCK for DDR400 at tCK=5ns; distributed refresh
Self refresh current; CKE =< 0.2V; External clock on; tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400.
Operating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
13.0 Input/Output Capacitance
( TA= 25°C, f=100MHz)
Parameter
Symbol
Min
Max DeltaCap(max) Unit Note
Input capacitance
(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
2
3
0.5 pF 4
Input capacitance( CK, CK )
CIN2
2
3
0.25 pF 4
Data & DQS input/output capacitance
Input capacitance(DM for x4/8, UDM/LDM for x16)
COUT
CIN3
4
4
5
5
pF 1,2,3,4
0.5
pF 1,2,3,4
Note :
1.These values are guaranteed by design and are tested on a sample basis only.
w2.wAwlth.oDuagthaDShMeiest4aUn .incopumt -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. For DDR266 and DDR333 VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +0.25V+0.2V. For DDR400, VDDQ = +2.6V +0.1V,
VDD = +2.6V +0.1V. For all devices, f=100MHz, tA=25°C, Vout(dc) = VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins -
reflecting the fact that they are matched in loading (to facilitate trace matching at the board level).
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Rev. 1.1 November 2008

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