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PDF CY14C101I Data sheet ( Hoja de datos )

Número de pieza CY14C101I
Descripción 1-Mbit (128 K X 8) Serial (I2C) nvSRAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY14C101I
PRELIMINARY
CY14B101I, CY14E101I
1 Mbit (128K x 8) Serial (I2C) nvSRAM
with Real Time Clock
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
Internally organized as 128 K x 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using
I2C
command (Software STORE) or HSB pin (Hardware STORE)
RorEbCyAIL2CL
to SRAM initiated on power-up (Power
command (Software RECALL)
Up
RECALL)
Automatic STORE on power-down with a small capacitor
I2C access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4 MHz operation
Average standby mode current of 250 uA
Sleep mode current of 8 uA
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 °C
Real Time Clock (RTC)
Full-featured RTC
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 uA (typical)
High-speed I2C interface
Industry standard 100 kHz and 400 kHz speed
Fast mode Plus: 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for 1/4, 1/2, or entire array
Industry standard configurations
Operating voltages:
• CY14C101I: VCC = 2.4 V to 2.6 V
• CY14B101I: VCC = 2.7 V to 3.6 V
• CY14E101I: VCC = 4.5 V to 5.5 V
Industrial temperature
16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14C101I/CY14B101I/CY14E101I combines a
1-Mbit nvSRAM[1] with a full-featured RTC in a monolithic
integrated circuit with serial I2C interface. The memory is
organized as 128 K words of 8 bits each. The embedded nonvol-
atile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cells provide highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down.
On power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL opera-
tions can also be initiated by the user through I2C commands.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Serial Number
8x8
Manufacture ID/
Product ID
Power Control
Block
Sleep
Memory Control Register
Command Register
Quantrum Trap
128 K x 8
SDA
SCL
A2, A1
WP
www.DataSheet4U.com
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
RTC Slave
Memory
Address and Data
Control
SRAM
128 K x 8
STORE
RECALL
X in
INT/SQW
Xout
RTC Control Logic
Registers
Counters
Note
1. Serial (I2C) nvSRAM will be referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-54391 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 21, 2011
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CY14C101I pdf
PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Figure 2. System Configuration using Serial (I2C) nvSRAM
Microcontroller
Vcc
SDA
RPmin = (VCC - VOLmax) / IOL
RPmax = tr / Cb
SCL
A1 SCL
A2 SDA
WP
Vcc
A1 SCL
A2 SDA
WP
Vcc
A1 SCL
A2 SDA
WP
CY14X101I
CY14X101I
CY14X101I
Data Validity
#0 #1
#3
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH: START and STOP condition. The
START and STOP conditions are generated by the master to
signal the beginning and end of a communication sequence on
the I2C bus.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I2C begins
with the master generating a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
If a Repeated START condition is generated instead of a STOP
condition, the bus continues to be busy. The ongoing transaction
on the I2C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SCL
www.DataSheet4U.com
S
START Condition
SDA
P
STOP Condition
SCL
Document #: 001-54391 Rev. *C
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CY14C101I arduino
PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Read Operation
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
In case of the Control Register Slave, whenever a burst read is
performed such that it flows to a non-existent address, the reads
operation loops back to 0x00. This is applicable, in particular, for
the Command Register.
Read operation can be ended using the following methods:
1. The master issues a NACK on the ninth clock cycle followed
by a STOP or a Repeated START condition on the tenth clock
cycle.
2. The master generates a STOP or Repeated START condition
on the ninth clock cycle.
More details on write instruction are provided in the section
“Memory Slave Access” on page 11.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform read or write operations from nvSRAM.
Write nvSRAM
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x00000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after nvSRAM receives all the
eight data bits. The nvSRAM sends an ACK signal after a
successful write operation. A write operation may be terminated
by the master by generating a STOP condition or a Repeated
START operation. If the master desires to abort the current write
operation without altering the memory contents, this should be
done using a START/STOP condition prior to the eighth data bit.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and the address counter is
not incremented.
Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
By Master
SDA Line
By nvSRAM
S
T
A
R Memory Slave Address
T
S 1 0 1 0 A2 A1 A16 0
A
Address MSB
Address LSB
AA
Data Byte
S
T
0
P
P
A
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
By Master
S
T
A
R Memory Slave Address
T
wwwS.DDAaLtinaeSheeSt4U1 .c0om1 0 A2 A1 A16 0
By nvSRAM
A
Address MSB
Address LSB
AA
Data Byte 1
A
Data Byte N
S
T
0
P
P
A
Document #: 001-54391 Rev. *C
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