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PDF CY14B512Q2 Data sheet ( Hoja de datos )

Número de pieza CY14B512Q2
Descripción 512-Kbit (64 K X 8) Serial (SPI) nvSRAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY14B512Q1
CY14B512Q2
CY14B512Q3
512-Kbit (64 K × 8) Serial (SPI) nvSRAM
Features512-Kbit (64 K × 8) Serial (SPI) nvSRAM
512-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 64 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14B512Q1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
High speed serial peripheral interface (SPI)
40 MHz clock rate
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4,1/2, or entire array
Low power consumption
Single 3 V +20%, –10% operation
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
Industrial temperature
CY14B512Q1 has identical pin configuration to industry
standard 8-pin NV memory
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B512Q1/CY14B512Q2/CY14B512Q3
combines a 512-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B512Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B512Q1
No
Yes
CY14B512Q2
Yes
Yes
CY14B512Q3
Yes
Yes
No No Yes
Logic Block Diagram
VCC
VCAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
64 K X 8
SRAM Array
64 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
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SI
Instruction
register
Address
Decoder
A0-A15
D0-D7
Data I/O register
SO
Note
1. This device will be referred to as nvSRAM throughout the document.
Status Register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-53873 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 12, 2011
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CY14B512Q2 pdf
CY14B512Q1
CY14B512Q2
CY14B512Q3
Device Operation
CY14B512Q1/CY14B512Q2/CY14B512Q3 is a 512-Kbit
nvSRAM memory with a nonvolatile element in each memory
cell. All the reads and writes to nvSRAM happen to the SRAM
which gives nvSRAM the unique capability to handle infinite
writes to the memory. The data in SRAM is secured by a STORE
sequence taht transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (VCAP) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
The 512-Kbit memory array is organized as 64 K words × 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the chip select (CS) pin and
accessed through serial input (SI), serial output (SO), and serial
clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (one quarter,
one half, or full array) using BP0 and BP1 pins in the Status
Register. Further, the HOLD pin can be used to suspend any
serial communication without resetting the serial sequence.
CY14B512Q1/CY14B512Q2/CY14B512Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their
application. The feature summary is given in Table 2.
Table 2. Feature Summary
Feature
CY14B512Q1 CY14B512Q2 CY14B512Q3
WP Yes No Yes
VCAP
HSB
No Yes Yes
No No Yes
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No
Yes Yes
Power-Up RECALL
Yes
Yes
Yes
Hardware STORE
No
No Yes
Software STORE
Yes
Yes
Yes
Software RECALL
Yes
Yes
Yes
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the memory access
section of SPI protocol description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and two bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the memory access
section of SPI protocol description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated,
read/write
to
CY14B512Q1/CY14B512Q2/CY14B512Q3 is inhibited until the
cycle is completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
Document #: 001-53873 Rev. *E
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CY14B512Q2 arduino
CY14B512Q1
CY14B512Q2
CY14B512Q3
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
SCK
01 23 4 5 6 701 2 3 4 5 6 7
Opcode
Data in
SI 0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X
MSB
LSB
SO HI-Z
Write Protection and Block Protection
CY14B512Q1/CY14B512Q2/CY14B512Q3 provides features
for both software and hardware write protection using WRDI
instruction and WP. Additionally, this device also provides block
protection mechanism through BP0 and BP1 pins of the Status
Register.
The Write Enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR
and WRITE) and nvSRAM special instruction (STORE,
RECALL, ASENB, and ASDISB) need the write to be enabled
(WEN bit = ‘1’) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the Write Disable state. The
following WRITE, WRSR, or nvSRAM special instruction must
therefore be preceded by a Write Enable instruction. If the device
is not Write Enabled (WEN = ‘0’), it ignores the write instructions
and returns to the standby state when CS is brought HIGH. A
new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR or WRITE)
or nvSRAM special instruction (STORE, RECALL, ASENB, and
ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to
provide protection from any inadvertent writes. Therefore,
WREN instruction must be used before a new write instruction is
issued.
Figure 9. WREN Instruction
CS
SCK
01 234567
SI 0 0 0 0 0 1 1 0
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SO
HI-Z
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
CS
SCK
01 234567
SI 0 0 0 0 0 1 0 0
SO HI-Z
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 6 shows the function of
block protect bits.
Table 6. Block Write Protect Bits
Level
Status Register
Bits Array Addresses Protected
BP1 BP0
0 00
None
1 (1/4)
0
1
0xC000-0xFFFF
2 (1/2)
1
0
0x8000-0xFFFF
3 (All)
1
1
0x0000-0xFFFF
Document #: 001-53873 Rev. *E
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