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PDF CY14B104LA Data sheet ( Hoja de datos )
| Número de pieza | CY14B104LA | |
| Descripción | 4-Mbit (512 K X 8/256 K X 16) nvSRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY14B104LA, CY14B104NA
4-Mbit (512 K × 8/256 K × 16) nvSRAM
Features
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512 K × 8 (CY14B104LA) or 256 K ×
16 (CY14B104NA)
■ Hands off automatic STORE on power-down with only a small
capacitor
■ STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or AutoStore on power-down
■ RECALL to SRAM initiated by software or power-up
■ Infinite read, write, and recall cycles
■ 1 million STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3 V +20%, -10% operation
■ Industrial temperature
■ Packages
❐ 44-/54-pin thin small outline package (TSOP II)
❐ 48-ball fine-pitch ball grid array (FBGA)
■ Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104LA/CY14B104NA is a fast static RAM
(SRAM), with a nonvolatile element in each memory cell. The
memory is organized as 512 K bytes of 8 bits each or 256 K
words of 16 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram[1, 2, 3]
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Notes
1. Address A0 - A18 for ×8 configuration and Address A0 - A17 for ×16 configuration.
2. Data DQ0 - DQ7 for ×8 configuration and Data DQ0 - DQ15 for ×16 configuration.
3. BHE and BLE are applicable for ×16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-49918 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2011
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CY14B104LA, CY14B104NA
Device Operation
The CY14B104LA/CY14B104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104LA/CY14B104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 1 million STORE
operations. Refer to the Truth Table For SRAM Operations on
page 17 for a complete description of read and write modes.
SRAM Read
The CY14B104LA/CY14B104NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-18 or A0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid (tSD time) before
the end of a WE controlled write or before the end of an CE
controlled write. The Byte Enable inputs (BHE, BLE) determine
which bytes are written, in the case of 16-bit words. It is recom-
mended that OE be kept HIGH during the entire write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoStore Operation
The CY14B104LA/CY14B104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by the HSB; Software STORE activated by an
address sequence; AutoStore on device power-down. The
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the
CY14B104LA/CY14B104NA.
wwwD.uDriantgaSahneoertm4Ua.lcoopmeration, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note
8. HSB pin is not available in 44-TSOP II (x16) package.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 7. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
VCC
0.1 uF
VCC
WE VCAP
VSS
VCAP
Hardware STORE Operation
The CY14B104LA/CY14B104NA provides the HSB[8] pin to
control and acknowledge the STORE operations. The HSB pin
is used to request a hardware STORE cycle. When the HSB pin
is driven LOW, the CY14B104LA/CY14B104NA conditionally
initiates a STORE operation after tDELAY. An actual STORE cycle
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 kΩ weak pull-up resistor) that is inter-
nally driven LOW to indicate a busy condition when the STORE
(initiated by any means) is in progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 kΩ pull-up
resistor.
Document #: 001-49918 Rev. *H
Page 5 of 24
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CY14B104LA, CY14B104NA
AC Switching Characteristics
Parameters
Cypress
Parameter
Alt
Parameter
SRAM Read Cycle
tACE
tRC[15]
tAA[16]
tACS
tRC
tAA
tDOE
tOHA[16]
tLZCE[17, 18]
tHZCE[17, 18]
tLZOE[17, 18]
tHZOE[17, 18]
tPU[17]
tPD[17]
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
tDBE
tLZBE[17]
tHZBE[17]
-
-
-
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE[17, 18,19]
tLZWE[17, 18]
tBW
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
-
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
20 ns
Min Max
– 20
20 –
– 20
– 10
3–
3–
–8
0–
–8
0–
– 20
– 10
0–
–8
20 –
15 –
15 –
8–
0–
15 –
0–
0–
–8
3–
15 –
25 ns
Min Max
– 25
25 –
– 25
– 12
3–
3–
– 10
0–
– 10
0–
– 25
– 12
0–
– 10
25 –
20 –
20 –
10 –
0–
20 –
0–
0–
– 10
3–
20 –
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled[15, 16, 20]
tRC
Address
Address Valid
tAA
45 ns
Min Max
– 45
45 –
– 45
– 20
3–
3–
– 15
0–
– 15
0–
– 45
– 20
0–
– 15
45 –
30 –
30 –
15 –
0–
30 –
0–
0–
– 15
3–
30 –
Data Output
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Previous Data Valid
tOHA
Output Data Valid
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE, OE and BHE / BLE LOW.
17. These parameters are guaranteed by design but not tested.
18. Measured ±200 mV from steady state output voltage.
19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
20. HSB must remain HIGH during read and write cycles.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 001-49918 Rev. *H
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| PDF Descargar | [ Datasheet CY14B104LA.PDF ] | |
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