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PDF S11156-2048 Data sheet ( Hoja de datos )
| Número de pieza | S11156-2048 | |
| Descripción | Back-thinned CCD image sensors | |
| Fabricantes | Hamamatsu | |
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CCD linear image sensors
S11155-2048 S11156-2048
Back-thinned CCD image sensors with
electronic shutter function
The S11155-2048 and S11156-2048 are back-thinned CCD linear image sensors with an internal electronic shutter for spec-
trometers. These image sensors use a resistive gate structure that allows high-speed transfer. Each pixel has a lengthwise size
needed by spectrometers but ensures readout with low image lag.
Features
Built-in electronic shutter
Minimum integration time: 30 μs
High sensitivity from the ultraviolet region
(spectral response range: 200 to 1100 nm)
Readout speed: 10 MHz max.
Image lag: 0.1% typ.
Applications
Spectrometers
Image readout
General ratings
Parameter
Pixel size
Number of total pixels
Number of active pixels
Active area
Horizontal clock phase
Output circuit
Package
Window*1
S11155-2048
S11156-2048
14 (H) × 500 (V) μm
14 (H) × 1000 (V) μm
2068 (H) × 1 (V)
2048 (H) × 1 (V)
28.672 (H) × 0.500 (V) mm
28.672 (H) × 1.000 (V) mm
2-phase
Two-stage MOSFET source follower
24-pin ceramic DIP (refer to dimensional outline)
Quartz glass
*1: Temporary window type (ex. S11155-2048N) is available upon request.
Resistive gate structure
In ordinary CCDs, one pixel contains multiple
electrodes and a signal charge is transferred by
applying different clock pulses to those elec-
trodes [Figure 1]. In resistive gate structures,
a single high-resistance electrode is formed in
the active area, and a signal charge is trans-
ferred by means of a potential slope that is
created by applying different voltages across
wwwta.DhreeaaetaliemScahtrgoeedeets4e[UnFsig.ocurorewmh2i]c.hCiosmupsaerdedastoa
a CCD
linear
sensor by line binning, a one-dimensional CCD
having a resistive gate structure in the active
area offers higher speed transfer, allowing
readout with low image lag even if the pixel
height is large.
[Figure 1] Schematic diagram and potential
of ordinary 2-phase CCD
P1V P2V P1V P2V
N- N N- N N- N N- N
P
[Figure 2] Schematic diagram and potential
of resistive gate structure
REGL
REGH STG TG
Resistive gate
P+ N N- N
P
KMPDC0320EA
Potential slope
KMPDC0321EB
www.hamamatsu.com
1
1 page  
CCD linear image sensors
S11155-2048, S11156-2048
Timing chart
Non-MPP operation
ARG
REGH, REGL (REGH: -3 V, REGL: -5.5 V)
Tpwv Tovr
1 line output period
Tpwar
(electronic shutter: closed)
Tinteg
(electronic shutter: open)
TG
Tpwh, Tpws
P1H
1
2
3..2067
2068
P2H
SG
Tpwr
RG
OS
D1 D2
D19 D20
D3..D10, S1...S2048, D11..D18
ARG
TG
P1H, P2H*17
SG
RG
TG - P1H
Parameter
Pulse width
Rise and fall times
Pulse width
Rise and fall time
Pulse width
Rise and fall time
Duty ratio
Pulse width
Rise and fall time
Duty ratio
Pulse width
Rise and fall time
Overlap time
Integration time
Symbol
Tpwar
Tprar, Tpfar
Tpwv
Tprv, Tpfv
Tpwh
Tprh, Tpfh
-
Tpws
Tprs, Tpfs
-
Tpwr
Tprr, Tpfr
Tovr
Tinteg
*17: Symmetrical clock pulses should be overlapped at 50% of maximum amplitude.
Min.
1
200
30
20
50
10
40
50
10
40
5
5
1
30
Typ.
-
-
-
-
100
-
50
100
-
50
15
-
2
-
Max.
-
-
-
-
-
-
60
-
-
60
-
-
-
-
KMPDC0340EB
Unit
μs
ns
μs
ns
ns
ns
%
ns
ns
%
ns
ns
μs
μs
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet S11156-2048.PDF ] | |
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