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PDF CBTL06DP211 Data sheet ( Hoja de datos )
| Número de pieza | CBTL06DP211 | |
| Descripción | DisplayPort Gen1 2 : 1 multiplexer | |
| Fabricantes | NXP Semiconductors | |
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CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
Rev. 1 — 21 February 2011
Product data sheet
1. General description
CBTL06DP211 is a multi-channel high-speed multiplexer meant for DisplayPort (DP)
v1.1a or Embedded DisplayPort applications operating at data rate of 1.62 Gbit/s or
2.7 Gbit/s. It is designed using NXP proprietary high-bandwidth pass-gate technology and
it can be used for 1 : 2 switching or 2 : 1 multiplexing of four high-speed differential
AC-coupled DP channels. Further, it is capable of switching/multiplexing of Hot Plug
Detect (HPD) signal as well as Auxiliary (AUX) and Display Data Channel (DDC) signals.
In order to support GPUs/CPUs that have dedicated AUX and DDC I/Os, CBTL06DP211
provides an additional level of multiplexing of AUX and DDC signals delivering true
flexibility and choice.
CBTL06DP211 consumes very low current in operational mode (less than 1 mA typical)
and provides for a shutdown function (ultra low current consumption less than 10 μA) to
support power-sensitive or battery-powered applications. It is designed for delivering
optimum performance at DP data rates of 1.62 Gbit/s and 2.7 Gbit/s.
A typical application of CBTL06DP211 is on motherboards where one of two GPU display
sources needs to be selected to connect to a display sink device or connector. A controller
chip selects which path to use by setting a select signal HIGH or LOW. Due to the
non-directional nature of the signal paths (which use high-bandwidth pass-gate
technology), the CBTL06DP211 can also be used in the reverse topology, e.g., to connect
one display source device to one of two display sink devices or connectors.
Optionally, the CBTL06DP211 can be used in conjunction with an HDMI/DVI level shifter
device (PTN3360A/B or PTN3360D) to allow for DisplayPort as well as HDMI/DVI
connectivity.
2. Features and benefits
www.DataSheet4U.com
1 : 2 switching or 2 : 1 multiplexing of DisplayPort (v1.1a - 1.62 Gbit/s or 2.7 Gbit/s)
4 high-speed differential channels with 2 : 1 multiplexing/switching for DisplayPort
signals
1 channel with 4 : 1 multiplexing/switching for AUX differential signals and DDC
single-ended clock and data signals
1 channel with 2 : 1 multiplexing/switching for single-ended HPD signals
High-bandwidth analog pass-gate technology
Very low lane intra-pair skew (5 ps typical)
Very low inter-pair skew (< 180 ps)
Switch/multiplexer position select CMOS input
Shutdown mode CMOS input
Shutdown mode delivers ultra low power consumption
1 page  
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
6.2 Pin description
Table 2. Pin description
Symbol
Ball Type
GPU_SEL
A1 3.3 V low-voltage CMOS
single-ended input
DDC_AUX_SEL C2
3.3 V low-voltage CMOS
single-ended input
XSD
B7
TST0
G2
IN1_0+
B4
IN1_0−
A4
IN1_1+
B5
IN1_1−
A5
IN1_2+
B6
IN1_2−
A6
IN1_3+
A8
IN1_3−
A9
IN2_0+
B8
IN2_0−
B9
IN2_1+
D8
IN2_1−
D9
IN2_2+
E8
IN2_2−
E9
IN2_3+
F8
IN2_3−
F9
OUT_0+
B2
OUT_0−
B1
OUT_1+
D2
OUT_1−
D1
OUT_2+
E2
OUT_2−
E1
OUT_3+
F2
OUT_3−
F1
www.ADUaXta1S+heet4U.com H9
AUX1−
J9
AUX2+
H6
AUX2−
J6
3.3 V low-voltage CMOS
single-ended input
3.3 V low-voltage CMOS
single-ended input
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
Description
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
Selects between DDC and AUX paths. When HIGH, the
DDC_CLKn and DDC_DATn I/Os are connected to their respective
AUX terminals. When LOW, the AUX+ and AUX− I/Os are
connected to their respective AUX terminals.
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting) and supply current consumption is minimized.
Test pin for NXP use only. Should be tied to ground in normal
operation.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
CBTL06DP211
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2011
© NXP B.V. 2011. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
CBTL06DP211
DisplayPort Gen1 2 : 1 multiplexer
11. Application information
11.1 Special considerations
Certain cable or dongle misplug scenarios make it possible for a 5 V input condition to
occur on pins AUX+ and AUX−, as well as HPDIN. When AUX+ and AUX− are connected
through a minimum of 2.2 kΩ resistor each, the CBTL06DP211 will sink current but will not
be damaged. Similarly, HPDIN may be connected to 5 V via at least a 1 kΩ resistor.
(Correct functional operation to specification is not expected in these scenarios.) The
latter also prevents the HPDIN input from loading down the system HPD signal when
power to the CBTL06DP211 is off.
www.DataSheet4U.com
CBTL06DP211
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2011
© NXP B.V. 2011. All rights reserved.
11 of 18
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