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PDF X76F101 Data sheet ( Hoja de datos )

Número de pieza X76F101
Descripción Secure SerialFlash
Fabricantes IC MICROSYSTEMS 
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No Preview Available ! X76F101 Hoja de datos, Descripción, Manual

This X76F101 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
1K X76F101
ICmicTM
IC MICROSYSTEMS
128 x 8 bit
Secure SerialFlash
FEATURES
•64-bit Password Security
•One Array (112 Bytes) Two Passwords
—Read Password
—Write Password
•Programmable Passwords
•32-bit Response to Reset (RST Input)
•8 byte Sector Write mode
•1MHz Clock Rate
•2 wire Serial Interface
•Low Power CMOS
—3.0 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
•High Reliability Endurance:
—100,000 Write Cycles
•Data Retention: 100 years
•Available in:
—8 lead PDIP, SOIC, MSOP and ISO Card
—SmartCard Module
DESCRIPTION
The X76F101 is a Password Access Security Supervisor,
containing one 896-bit Secure Serial Flash array. Access
to the memory array can be controlled by two 64-bit
passwords. These passwords protect read and write
operations of the memory array.
The X76F101 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirectional
data input and output (SDA). Access to the
device is controlled through a chip select (CS) input,
allowing any number of devices to share the same bus.
The X76F101 also features a synchronous response to reset
providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
The X76F101 utilizes Xicor’s proprietary Direct WrTitMe
cell, providing a minimum endurance of 100,000 cycles and
a minimum data retention of 100 years.
Functional Diagram
CS
SCL
SDA
Interface
Logic
RST
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CHIP ENABLE
DATA TRANSFER
ARRAY ACCESS
ENABLE
PASSWORD ARRAY
AND PASSWORD
VERIFICATION LOGIC
RESET
RESPONSE REGISTER
8K BYTE
SerialFlash ARRAY
ARRAY 0
(PASSWORD PROTECTED)
112 Byte
32 BYTE
SerialFlash ARRAY
ARRAY 1
(PASSWORD PROTECTED)
RETRY COUNTER
7025 FM 01
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
7065 -1.1 4/17/98 T2/C0/D0 SH
1
Characteristics subject to change without notice

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X76F101 pdf
X76F101
followed by the new command code of 8 bits (1st byte of the
protocol.) If the X76F101 is still busy with the
nonvolatile write operation, it will issue a “no-ACK” in
response. If the nonvolatile write operation has
completed, an “ACK” will be returned and the host can then
proceed with the rest of the protocol.
Password ACK Polling Sequence
PASSWORD LOAD
COMPLETED
ENTER ACK POLLING
Data ACK Polling Sequence
WRITE SEQUENCE
COMPLETED
ENTER ACK POLLING
ISSUE START
ISSUE NEW
COMMAND
CODE
ISSUE START
ISSUE
PASSWORD
ACK COMMAND
ACK
RETURNED?
YES
NO
ACK
RETURNED?
NO
PROCEED
YES
PROCEED
After the password sequence, there is always a nonvolatile
write cycle. This is done to discourage random
guesses of the password if the device is being tampered with.
In order to continue the transaction, the X76F101
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
with regular Acknowledge polling the user can either time out
for 10ms, and then issue the ACK polling once, or
continuously loop as described in the flow.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
response to the password ACK polling sequence is over.
If the password that was inserted was incorrect, then a “no
www.DAaCtaKShweiellt4bUe .rceotmurned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed.
READ OPERATIONS
Read operations are initiated in the same manner as write
operations but with a different command code.
Sector Read
With sector read, a sector address is supplied with the read
command. Once the password has been
acknowledged data may be read from the sector. An
acknowledge must follow each 8-bit data transfer. A read
operation always begins at the first byte in the sector, but may
stop at any time. Random accesses to the array are
not possible. Continuous reading from the array will return
data from successive sectors. After reading the
last sector in the array, the address is automatically set to the
first sector in the array and data can continue to be
read out. After the last bit has been read, a stop condition is
generated without sending a preceding acknowledge.
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X76F101 arduino
X76F101
RST Timing Diagram – Response to a Synchronous Reset
tSR
CS
RST
tNOL
CLK
I/O
tRST
1st
clk
pulse
tRDV
tNOL
tSU:RST
tHIGH_RST
2nd
clk
pulse
tCDV
DATA BIT (1)
tLOW_RST
3rd
clk
pulse
DATA BIT (2)
CS
RST
CLK
I/O
DATA BIT (N)
DATA BIT (N+1)
tDHZ
(N+2)
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
80
RMAX
60
40
20 RMIN
20 40 60 80 100
Bus capacitance in pF
R
MIN
V
= ---IC---C---M---A---X---------=-- 1.8KΟ
OLMIN
R
MAX
t
= C-----R------------
BUS
tR = maximum allowable SDA rise time
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