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PDF CAT34AC02 Data sheet ( Hoja de datos )
| Número de pieza | CAT34AC02 | |
| Descripción | 2K-Bit SMBus EEPROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Preliminary Information
CAT34AC02
2K-Bit SMBus EEPROM for ACR Card Configuration
FEATURES
ALOGEN FR
LEA
D
F
R
E
E
TM
s 400 kHz (5V) and 100 kHz (1.8V) SMBus
compatible
s 1.8 to 6.0 volt operation
s Low power CMOS technology
– zero standby current
s 16-byte page write buffer
s Industrial, automotive and extended
temperature ranges
s Self-timed write cycle with auto-clear
s 1,000,000 program/erase cycles
s 100 year data retention
s 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages
s 256 x 8 memory organization
s Hardware write protect
DESCRIPTION
The CAT34AC02 is a 2K-bit Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT34AC02 features a
16-byte page write buffer. The device operates via the
SMBus serial interface for ACR card configuration and
is available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
BLOCK DIAGRAM
EXTERNAL LOAD
A0
A1
A2
VSS
1
2
3
4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
TSSOP Package (U, Y)
MSOP Package (R, Z)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
18
27
36
45
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
www.DaStaCShLeet4U.com Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1025, Rev. E
1 page  
CAT34AC02
SERIAL BUS PROTOCOL
The following defines the features of the ACR Serial bus
protocol:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34AC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1011 for the CAT34AC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
eight CAT34AC02 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT34AC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34AC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT34AC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT34AC02 begins a READ mode, it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT34AC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
www.DFatiagSuhreeet54U. .Scolamve Address Bits
ACKNOWLEDGE
1 0 1 1 A2 A1 A0 R/W
DEVICE ADDRESS
5 Doc No. 1025, Rev. E
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CAT34AC02.PDF ] | |
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