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PDF NLSX3018 Data sheet ( Hoja de datos )
| Número de pieza | NLSX3018 | |
| Descripción | 8-Bit 100 Mb/s Configurable Dual-Supply Level Translator | |
| Fabricantes | ON Semiconductor | |
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NLSX3018
8-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3018 is a 8−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O VCC− and I/O
VL−ports are designed to track two different power supply rails, VCC
and VL respectively. The VCC supply rail is configurable from 1.3 V
to 4.5 V while the VL supply rail is configurable from 0.9 V to (VCC
− 0.4) V. This allows lower voltage logic signals on the VL side to be
translated into higher voltage logic signals on the VCC side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both VCC and VL. The EN signal is designed to track
VL.
Features
• Wide High−Side VCC Operating Range: 1.3 V to 4.5 V
Wide Low−Side VL Operating Range: 0.9 V to (VCC − 0.4) V
• High−Speed with 100 Mb/s Guaranteed Date Rate for VL > 1.6 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Powerup Sequencing
• Small packaging: 4.0 mm x 2.0 mm UQFN20
• This is a Pb−Free Device
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
PIN ASSIGNMENT
I/O VL1 1
I/O VL2 2
I/O VL3
I/O VL4
VL
EN
3
4
5
6
I/O VL5 7
www.DataSheet4U.Ic/OomVL6 8
I/O VL7 9
I/O VL8 10
20 I/O VCC1
19 I/O VCC2
18 I/O VCC3
17 I/O VCC4
16 VCC
15 GND
14 I/O VCC5
13 I/O VCC6
12 I/O VCC7
11 I/O VCC8
(Top View)
http://onsemi.com
UQFN20
MU SUFFIX
CASE 517AK
MARKING
DIAGRAMS
LAM
G
LA = Specific Device Code
M = Date Code
G = Pb−Free Package
20
SOIC−20
DW SUFFIX
CASE 751D
NLSX3018
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
TSSOP−20
DT SUFFIX
CASE 948E
NLSX
3018
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 0
1
Publication Order Number:
NLSX3018/D
1 page  
NLSX3018
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIHC
I/O VCC Input HIGH
Voltage
VILC
I/O VCC Input LOW
Voltage
VIHL
I/O VL Input HIGH
Voltage
Test Conditions
(Note 1)
−405C to +855C
VCC (V)
(Note 2)
VL (V)
(Note 3)
Typ
Min (Note 4) Max
1.3 to 4.5 0.9 to (VCC – 0.4)
0.8 *
VCC
−
−
1.3 to 4.5 0.9 to (VCC – 0.4)
−
− 0.2 *
VCC
1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL
−
−
Unit
V
V
V
VILL I/O VL Input LOW
Voltage
1.3 to 4.5 0.9 to (VCC – 0.4)
−
− 0.2 * VL V
VIH Control Pin Input HIGH
Voltage
TA = +25°C
1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL
−
−V
VIL Control Pin Input LOW
Voltage
TA = +25°C
1.3 to 4.5 0.9 to (VCC – 0.4)
−
− 0.2 * VL V
VOHC
VOLC
VOHL
I/O VCC Output HIGH
Voltage
I/O VCC Output LOW
Voltage
I/O VL Output HIGH
Voltage
I/O VCC Source Current =
20 mA
I/O VCC Sink Current = 20 mA
1.3 to 4.5 0.9 to (VCC – 0.4)
1.3 to 4.5 0.9 to (VCC – 0.4)
0.8 *
VCC
−
I/O VL Source Current = 20 mA 1.3 to 4.5 0.9 to (VCC – 0.4) 0.8 * VL
−
−
−
−
0.2 *
VCC
−
V
V
V
VOLL I/O VL Output LOW
Voltage
I/O VL Sink Current = 20 mA 1.3 to 4.5 0.9 to (VCC – 0.4)
−
− 0.2 * VL V
1. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
POWER CONSUMPTION
Symbol
Parameter
Test Conditions
(Note 5)
VCC (V)
(Note 6)
VL (V)
(Note 7)
IQ−VCC Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4)
VCC I/O VCCn = VCC or I/O VLn = VL and Io = 0
IQ−VL Supply Current from EN = VL; I/O VCCn = 0 V, I/O VLn = 0 V, 1.3 to 3.6 0.9 to (VCC – 0.4)
VL I/O VCCn = VCC or I/O VLn = VL and Io = 0
EN = VL, I/O VCCn = 0 V, I/O VLn = 0 V,
I/O VCCn = VCC or I/O VLn = (VCC −
0.2 V) and Io = 0
< (VCC – 0.2)
ITS−VCC VCC Tristate Output
Mode Supply
Current
EN = 0 V
1.3 to 3.6 0.9 to (VCC – 0.4)
−405C to +855C
Min Typ Max
− − 1.0
− − 1.0
− − 2.0
− − 1.0
Unit
mA
mA
mA
ITS−VL
VL Tristate Output
Mode Supply
Current
IOZ I/O Tristate Output
www.DataSheet4UMC.uocrodreemnLteakage
EN = 0 V
EN = 0 V
EN = 0 V
EN = 0 V
1.3 to 3.6 0.9 to (VCC – 0.4)
VCC − 0.2
1.3 to 3.6 0.9 to (VCC – 0.4)
VCC – 0.2
−
−
−
−
− 0.2 mA
− 2.0
− 0.15 mA
− 2.0
IEN Output Enable Pin
Input Current
−
1.3 to 3.6 0.9 to (VCC – 0.4) −
− 1.0 mA
5. Normal test conditions are VEN = 0 V, CIOVCC = 15 pF and CIOVL = 15 pF, unless otherwise specified.
6. VCC is the supply voltage associated with the high voltage port, and VCC ranges from +1.3 V to 3.6 V.
7. VL is the supply voltage associated with the low voltage port. VL must be less than or equal to (VCC – 0.4) V during normal operation. However,
during startup and shutdown conditions, VL can be greater than (VCC – 0.4) V.
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5
5 Page 
NLSX3018
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
0.15 (0.006) T U S
2X L/2 20
L
PIN 1
IDENT
1
0.15 (0.006) T U S
C
D
0.100 (0.004)
−T− SEATING
PLANE
20X K REF
0.10 (0.004) M T U S V S
11
B
−U−
10
A
−V−
GH
J J1 ÍÍÍÍÍÍKK1 ÍÍÍ
SECTION N−N
N 0.25 (0.010)
M
N
F
DETAIL E
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
−W−
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
B 4.30 4.50 0.169 0.177
C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT
7.06
1
www.DataSheet4U.com
16X
0.36
16X
1.26
0.65
PITCH
DIMENSIONS: MILLIMETERS
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11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NLSX3018.PDF ] | |
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