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PDF IN80C52N Data sheet ( Hoja de datos )
| Número de pieza | IN80C52N | |
| Descripción | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER | |
| Fabricantes | Integral | |
| Logotipo |  |
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IN80C32N/IN80C52N
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
The 80C32/80C52 is a high-performance microcontroller fabricated with high-density
CMOS technology.
The 80C52 contains a 8k x 8 ROM , a 256 x 8 RAM , 32 I/O lines, three 16-bit
counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port
for either multi-processor communications, I/O expansion or full duplex UART, and on-
chip oscillator and clock circuits.
The device has two software selectable modes of power reduction idle mode and
power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial
port, and interrupt system to continue functioning. The power-down mode saves the RAM
contents but freezes the oscillator, causing all other chip functions to be inoperative.
FEATURES
PIN CONFIGURATIONS
• 8032/8052 compatible (MCS-51 family)
8k x 8 ROM (80C52)
ROMless (80C32)
256 x 8 RAM
Three 16-bit counter/timers
Full duplex serial channel
Boolean processor
• Memory addressing capability
64k ROM and 64k RAM
• Power control modes:
Idle mode
Power-down mode
• CMOS and TTL compatible
• Two speed ranges at VCC=5V
12 Mhz
16 Mhz
T 2 /PP11.0.0 1
40 Vcc
T 2E X /P 1 .1 2
3 9 P 0 .0 /A D 0
P 1 .2 3
3 8 P 0 .1 /A D 1
P 1 .3 4
3 7 P 0 .2 /A D 2
P 1 .4 5
3 6 P 0 .3 /A D 3
P 1 .5 6
3 5 P 0 .4 /A D 4
P 1 .6 7
3 4 P 0 .5 /A D 5
P 1 .7 8
3 3 P 0 .6 /A D 6
RST 9
P L A S T IC
3 2 P 0 .7 /A D 6
R xD /P 3 .0
10
DUAL
IN -L IN E
31 EA
PACKAGE
T xD /P 3.2
11
30 ALE
IN T 0/P 3.2
12
29 PSEN
IN T 1/P 3.3
13
2 8 P 2 .7 /A 15
T 0/P 3.4
14
2 7 P 2 .6 /A 14
T 1/P 3.5
15
2 6 P 2 .5 /A 13
W R /P36 16
2 5 P 2 .4 /A 12
R D /P 3 .7 1 7
2 4 P 2 .3 /A 11
XTAL2 18
2 3 P 2 .2 /A 10
XTAL1 19
2 2 P 2 .1 /A 9
Vss 20
2 1 P 2 .0 /A 8
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