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PDF PACVGA105 Data sheet ( Hoja de datos )
| Número de pieza | PACVGA105 | |
| Descripción | VGA Port Companion Circuit | |
| Fabricantes | California Micro Devices | |
| Logotipo |  |
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PACVGA105
VGA Port Companion Circuit
Features
• 7 channels of ESD protection designed to
meet IEC-1000-4-2 Level-4 ESD requirements
(8kV contact discharge)
• Very low loading capacitance from ESD protection
diodes at less than 5pF typical
• TTL to CMOS level-translating buffers for the
HSYNC and VSYNC lines
• Three independent supply pins (VCC, VRGB and
VAUX) to facilitate operation with sub-micron
Graphics Controller ICs
• High impedance pull-ups (50kΩ nominal to VAUX)
for HSYNC and VSYNC inputs
• Pull-up resistors (1.8kΩ nominal to VCC) for
DDC_CLK and DDC_DATA lines
• Compact 16-pin QSOP package
• Lead-free version available
Applications
• ESD protection and termination resistors for VGA
(video) port interfaces
• Desktop PCs
• Notebook computers
• LCD monitors
Product Description
The PACVGA105 incorporates 7 channels of ESD pro-
tection for signal lines commonly found in a VGA port
for PCs. ESD protection is implemented with current
steering diodes designed to safely handle the high
peak surge currents associated with the IEC-1000-4-2
Level-4 ESD Protection Standard (8kV contact dis-
charge). When the channels are subjected to an elec-
trostatic discharge, the ESD current pulse is diverted
via the protection diodes into the positive supply rails or
ground where they may be safely dissipated.
The upper ESD diodes for the R, G and B channels are
connected to a separate supply rail (VRGB) to facilitate
interfacing to graphics controller ICs with low voltage
supplies. The remaining channels are connected to the
main 5V rail (VCC). The lower diodes for the R, G and B
channels are also connected to a dedicated ground pin
(GNDA) to minimize crosstalk due to common ground
impedance.
Two non-inverting buffers are also included in this IC
for buffering the HSYNC and VSYNC signals from the
graphics controller IC. These buffers will accept TTL
input levels and convert them to CMOS output levels
that swing between GND and VCC. These drivers have
a nominal 60Ω output impedance to match the charac-
teristic impedance of the HSYNC and VSYNC lines of
the video cables typically used. The inputs of these
drivers also have high impedance pull-ups (50kΩ nom.)
pulling up to the VAUX rail. In addition, the
DDC_CLOCK and DDC_DATA channels have 1.8kΩ
resistors pulling these inputs up to the main 5V (VCC)
rail.
Simplified Electrical Schematic
VRGB
VCC
VAUX
R
www.DataSheet4U.comG
B
GNDA
1.8k 1.8k 50k 50k
DDC_CLK
DDC_DATA
HSYNC
VSYNC
GNDD
VSYNC_OUT
HSYNC_OUT
© 2004 California Micro Devices Corp. All rights reserved.
01/28/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846 L www.calmicro.com
1
1 page  
Application Information
PACVGA105
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Grn
Blue
VF** - VIDEO EMI Filter
SF** - SYNC EMI Filter
To Video
DAC VDD
5V
3.3V
0.2uF
0.2uF
4
VRGB
9,16
VCC
13
VAUX
2 HSYNC
14 VSYNC
10 DDC_DATA
12 DDC_CLK
8
GNDA
GNDD 3, 11
DIGITAL ANALOG
PACVGA105
GND GND
HSYNC_OUT 1
VSYNC_OUT 15
7R
6G
5B
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Green
Blue
Figure 1. Typical Connection Diagram
GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should ide-
ally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital signals
from injecting noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the
printed circuit board.
www.DataSheet4U.com
© 2004 California Micro Devices Corp. All rights reserved.
01/28/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: 408.263.3214
L Fax: 408.263.7846 L www.calmicro.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet PACVGA105.PDF ] | |
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