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PDF PCS1P2192A Data sheet ( Hoja de datos )
| Número de pieza | PCS1P2192A | |
| Descripción | VDP Multiple Pixel Clock Generator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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PCS1P2192A
VDP Multiple Pixel
Clock Generator
Features
• Generates multiple clock outputs from 20MHz
external reference clock
• Input frequency: 20MHz
• Output frequencies:
o Selectable CLKOUT:
108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz,
25MHz, 45MHz, and 40MHz
o REFOUT: 20MHz
• Operating Supply Voltage: 3.3V ± 0.3V
• Zero ppm frequency synthesis error on all clock
outputs
• 8-pin SOIC package
Product Description
The PCS1P2192A is a clock generator that generates
multiple selectable pixel clock outputs for Video Display
Panel applications from an external 20MHz reference
clock. The PLL based clock generator is specifically
designed to provide zero ppm frequency synthesis error
on all clock outputs. Various pixel clock rates are
selectable through frequency selection pins S[2:0] (Refer
to Frequency Selection Table) The device provides a
reference clock output additionally. Operating Supply
Voltage for this device is 3.3V ± 0.3V. The device is
available in an 8-pin SOIC package.
Application
PCS1P2192A is targeted towards Video Display Panel
(VDP) applications like VGA, SVGA, XGA, WXGA,
UXGA.
Block Diagram
VDD [S2: S0]
CLKIN
www.DataSheet4U.com
PLL
GND
CLKOUT
REFOUT
©2010 SCILLC. All rights reserved.
JANUARY 2010 – Rev. 2
Publication Order Number:
PCS1P2192/D
1 page  
PCS1P2192A
Typical Application Schematic
CLKIN
1 CLKIN
VDD
0Ω
0Ω VDD
0Ω
0Ω
2 GND
3 S0
4 S1
VDD 8
CLKOUT 7
REF 6
S2 5
VDD
0.01uF
GND
VDD
0Ω
0Ω
Use either pull-up or pull-down
0Ω Resistor with [S2:S0] for selection of
CLKOUT frequencies.
PCB Layout Recommendation
For optimum device performance, following guidelines are
recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power
supply noise. A 0.01µF decoupling capacitor should
be mounted on the component side of the board as
close to the VDD pin as possible. No vias should be
A typical layout is shown in the figure below.
GND
used between the decoupling capacitor and VDD pin.
The PCB trace to VDD pin and the ground via should
be kept as short as possible. All the VDD pins should
have decoupling capacitors.
• In an optimum layout all components are on the same
side of the board, minimizing vias through other
signal layers.
As short
as possible
VDD
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Rev. 2 | Page 5 of 7 | www.onsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PCS1P2192A.PDF ] | |
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