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PDF PCS3PS550A Data sheet ( Hoja de datos )
| Número de pieza | PCS3PS550A | |
| Descripción | General Purpose Peak EMI Reduction IC | |
| Fabricantes | ON Semiconductor | |
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PCS3PS550A
General Purpose Peak EMI
Reduction IC
Product Description
The PCS3PS550A is a versatile 2.3 V to 3.6 V, Timing−Safe™,
spectrum frequency modulator designed specifically for a wide range
of clock frequencies. The PCS3PS550A reduces electromagnetic
interference (EMI) at the clock source, allowing system wide
reduction of EMI of all clock dependent signals. The PCS3PS550A
allows significant system cost savings by reducing the number of
circuit board layers ferrite beads, shielding that are traditionally
required to pass EMI regulations.
Features
• LVCMOS Peak EMI reduction IC
• Input Clock Frequency: 18 MHz − 36 MHz
• Output Clock Frequency: 18 MHz − 36 MHz
• Eight different selectable Spread options
• Power Down option for power save
• Supply Voltage: 2.3 V − 3.6 V
• 8−pin WDFN , 2 mm x 2 mm (TDFN) Package
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• The PCS3PS550A is targeted towards consumer electronic
applications.
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MARKING
DIAGRAMS
1
WDFN8
CASE 511AQ
1 CAMG
G
CA = Specific Device Code
M = Date Code
G = Pb−Free Device
PIN CONFIGURATION
CLKIN 1
SR2 2
PD# 3
VSS 4
PCS3PS550A
8 VDD
7 SR0
6 SR1
5 ModOUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
July, 2010 − Rev. 1
1
Publication Order Number:
PCS3PS550A/D
1 page  
PCS3PS550A
VDDIN
R
C1
C2
M Clock
1 CLKIN
8
VDD
0.1mF
2.2mF
PCS3PS550A
VDD
SR2, SR1, SR0
Frequency Deviation
Selection Control
0W
0W
ModOUT 5
2,6,7 SR2/SR1/SR0
VSS
4
PD# 3
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Rs
ModOUT Clock
VDD
0W
Power Down
0 W Control
NOTE: Refer Pin Description table for Functionality details.
Figure 2. Typical Application Schematic
PCB Layout Recommendation
For optimum device performance, following guidelines are recommended.
• Dedicated VDD and GND planes.
• The device must be isolated from system power supply noise. A 0.1mF and a 2.2 mF decoupling capacitor should be
mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as short as possible.
All the VDD pins should have decoupling capacitors.
• In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.
A typical layout is shown in the figure
As short as
possible
CLKIN
SR2
PD#
VSS
R
VDD
As short as
possible
SR0
SGRN1 D
Modout
Rs
Figure 3.
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PCS3PS550A.PDF ] | |
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