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PDF GS880F36AT-8.5 Data sheet ( Hoja de datos )

Número de pieza GS880F36AT-8.5
Descripción 9Mb Synchronous Burst SRAMs
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS880F36AT-8.5 Hoja de datos, Descripción, Manual

GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
100-Pin TQFP
Commercial Temp
Industrial Temp
512K x 18, 256K x 32, 256K x 36
9Mb Synchronous Burst SRAMs
www.D5a.5taSnhsee8t4.5U.ncosm
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
Functional Description
Applications
The GS880F18/32/36AT is a 9,437,184-bit (8,388,608-bit for
x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing for Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with VSS connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880F18/32/36AT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
Flow Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
-250 -225 -200 -166 -150 -133 Unit
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
175 165 160 150 145 135 mA
200 190 180 170 165 150 mA
Rev: 1.03 11/2004
1/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

1 page




GS880F36AT-8.5 pdf
TQFP Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1, E3
E2
G
ADV
ADSP, ADSC
ZZ
LBO
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
www.DataSheet4U.com
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Data Input and Output pin
No Connect
Byte WriteWrites all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write EnableWrites all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.03 11/2004
5/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

5 Page





GS880F36AT-8.5 arduino
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
Simplified State Diagram with G
www.DataSheet4U.com
X
Deselect
WR
WR
X
First Write
CW
R
CR
W First Read X
CW CR
W
X
R
Burst Write
CR
CW
R
W Burst Read X
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.03 11/2004
11/23
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

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