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PDF KM736V799 Data sheet ( Hoja de datos )
| Número de pieza | KM736V799 | |
| Descripción | 128Kx36 Synchronous SRAM | |
| Fabricantes | Samsung Semiconductor | |
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KM736V799
128Kx36 Synchronous SRAM
Document Title
128Kx36-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No History
0.0 Initial draft
0.1 Change Undershoot spec
from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2)
Add Overshoot spec 4.6V(pulse width≤tCYC/2)
Change VIH max from 5.5V to VDD+0.5V
0.2
0.3
.
Change tCD from 3.2ns to 3.1ns at bin -50.
Change tOE from 3.2ns to 3.1ns at bin -50.
Change setup from 1.5ns to 1.4ns at bin -50.
Change tCYC from 5.5ns to 5.4ns at bin -55.
Change tCD from 3.5ns to 3.1ns at bin -55.
Change tOE from 3.5ns to 3.1ns at bin -55.
Change setup from 1.5ns to 1.4ns at bin -55.
0.4 Add tCYC 175Mhz.
Change ISB2 from 20mA to 30mA.
0.5 Modify DC characteristics( Input Leakage Current test Conditions)
form VDD=VSS to VDD to Max.
1.0 Final Release.
2.0 Add tCYC 225Mhz.
3.0 Add VDDQ Supply voltage( 2.5V )
4.0 Change tCD , tOE from 3.1ns to 2.8ns at bin -44.
Change tHZC max , tHZOE max from 3.0ns to 2.8ns at bin -44.
5.0 Add tCYC 250Mhz.
6.0 Change tAH, tSH, tDH, tWH, tADVH, tCSH from 0.5ns to 0.4ns at bin -40.
7.0 1. Change tAS, tSS, tDS, tWS, tADVS, tCSS from 1.4ns to 1.2ns at bin -44.
2. Change tAH, tSH, tDH, tWH, tADVH, tCSH from 0.5ns to 0.4ns at bin -44.
3. Change tAS, tSS, tDS, tWS, tADVS, tCSS from 1.2ns to 0.8ns at bin -40.
4. Change tAH, tSH, tDH, tWH, tADVH, tCSH from 0.4ns to 0.3ns at bin -40.
8.0 1. Change ISB value from 120mA to 130mA at -57
9.0 Remove 119BGA(7x17 Ball Grid Array Package) .
Draft Date
April . 14. 1998
April . 20. 1998
Remark
Preliminary
Preliminary
May . 23. 1998
Preliminary
May . 25. 1998
Preliminary
May . 30. 1998
Preliminary
June. 08. 1998
Preliminary
June. 15 . 1998
July. 10 . 1998
Dec. 02. 1998
Mar. 04. 1999
Final
Final
Final
Fianl
April. 10. 1999
May. 03. 1999
May. 10. 1999
Final
Final
Final
June. 24. 1999
Nov. 26. 1999
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - November 1999
Rev 9.0
www.DataSheet.in
1 page  
KM736V799
128Kx36 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED
HXXXL X X ↑
N/A
L LXLXX X ↑
N/A
LXHLXX X ↑
N/A
L LXXLX X ↑
N/A
LXHXL X X ↑
N/A
LHL LXX X ↑
External Address
LHLHLX L ↑
External Address
LHLHLX H ↑
External Address
XXXHHL H ↑
Next Address
HXXXHL H ↑
Next Address
XXXHHL L ↑
Next Address
HXXXHL L ↑
Next Address
XXXHHH H ↑
Current Address
HXXXHH H ↑
Current Address
XXXHHH L ↑
Current Address
HXXXHH L ↑
Current Address
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
WRITE TRUTH TABLE
GW
BW
WEa
WEb
WEc
WEd
OPERATION
HHX X X X
READ
HL HHHH
READ
HL L HHH
WRITE BYTE a
HL HL HH
WRITE BYTE b
HL HHL L
WRITE BYTE c and d
HLL LL L
WRITE ALL BYTEs
L XXXXX
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ OE I/O STATUS
Sleep Mode
HX
High-Z
Read
LL
LH
DQ
High-Z
Write
L X Din, High-Z
Deselected
LX
High-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
www.DataSheet.in
- 5 - November 1999
Rev 9.0
5 Page 
KM736V799
128Kx36 Synchronous SRAM
www.DataSheet.in
- 11 -
November 1999
Rev 9.0
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet KM736V799.PDF ] | |
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