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PDF KM736V790 Data sheet ( Hoja de datos )
| Número de pieza | KM736V790 | |
| Descripción | 128Kx36 Synchronous SRAM | |
| Fabricantes | Samsung Semiconductor | |
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KM736V790
128Kx36 Synchronous SRAM
Document Title
128Kx36-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No. History
Draft Date
Remark
0.0 Initial draft
December. 15. 1997 Preliminary
0.1 Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85,
Change 7.5 bin to 7.2
February. 02. 1998 Preliminary
0.2 Change speed bin from 60/67/75/85 to 72/85/10.
February. 06. 1998 Preliminary
0.3 Change DC characteristics VDD condition from 3.3V±5% to 3.3V+10%/-5% February. 12. 1998 Preliminary
Change Input/output leackage currant for ±1µA to ±2µA,
Insert Note 4 at AC timing characteristics.
Modify read timing & Power down cycle timing.
Change ISB2 value from 10mA to 20mA.
Remove Low power version.
0.4 Change Undershoot spec
from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2)
Add Overshoot spec 4.6V((pulse width≤tCYC/2)
Change VIN max from 5.5V to VDD+0.5V
April. 14. 1998
Preliminary
0.5 Change ISB2 value from 20mA to 30mA.
May. 13. 1998
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
Preliminary
0.6 Modify DC characteristics( Input Leakage Current test Conditions)
form VDD=VSS to VDD to Max.
May. 14. 1998
Preliminary
1.0 Final spec Release
May. 15. 1998
Final
2.0 Add VDDQ Supply voltage( 2.5V )
Dec. 02. 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - December 1998
Rev 2.0
www.DataSheet.in
1 page  
KM736V790
128Kx36 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED
HXXXLX X ↑
N/A
L LXLXX X ↑
N/A
L XHLXX X ↑
N/A
L LXXLX X ↑
N/A
L XHXLX X ↑
N/A
LHL LXX X ↑
External Address
LHLHLX L ↑
External Address
LHLHLX H ↑
External Address
XXXHHL H ↑
Next Address
HXXXHL H ↑
Next Address
XXXHHL L ↑
Next Address
HXXXHL L ↑
Next Address
XXXHHH H ↑
Current Address
HXXXHH H ↑
Current Address
XXXHHH L ↑
Current Address
HXXXHH L ↑
Current Address
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
WRITE TRUTH TABLE
GW
BW
WEa
WEb
WEc
WEd
HHXXXX
H L HHHH
HL LHHH
OPERATION
READ
READ
WRITE BYTE a
H L H L HH
HLHHL L
HL L L L L
LXXXXX
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ OE I/O STATUS
Sleep Mode
HX
High-Z
Read
LL
LH
DQ
High-Z
Write
L X Din, High-Z
Deselected
LX
High-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
www.DataSheet.in
- 5 - December 1998
Rev 2.0
5 Page 
KM736V790
128Kx36 Synchronous SRAM
www.DataSheet.in
- 11 -
December 1998
Rev 2.0
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet KM736V790.PDF ] | |
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