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PDF KM736V749 Data sheet ( Hoja de datos )

Número de pieza KM736V749
Descripción (KM736V749 / KM718V849) 128Kx36 & 256Kx18 Pipelined NtRAM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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KM736V749
KM718V849
128Kx36 & 256Kx18 Pipelined NtRAMTM
Document Title
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
Revision History
Rev. No.
History
0.0 1. Initial document.
0.1 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75
2. Changed DC condition at Icc and parameters
ISB1 ; from 10mA to 30mA,
ISB2 ; from 10mA to 30mA.
0.2 Add VDDQ Supply voltage( 2.5V I/O )
0.3 Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O.
1.0 Final spec Release.
2.0 Remove VDDQ Supply voltage( 2.5V I/O )
3.0 Add VDDQ Supply voltage( 2.5V I/O )
Draft Date
July.06. 1998
Oct. 10 . 1998
Dec. 10. 1998
Dec. 23. 1998
Jan. 29. 1999
Feb. 25. 1999
May. 13. 1999
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
www.DataSheet.in
- 1 - May 1999
Rev 3.0

1 page




KM736V749 pdf
KM736V749
KM718V849
128Kx36 & 256Kx18 Pipelined NtRAMTM
FUNCTION DESCRIPTION
The KM736V749 and KM718V849 are NtRAMTM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when
there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the
burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next
operation.
Clock Enable(CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous
inputs are ignored and the internal device registers will hold their previous values.
NtRAMTM latches external address and initiates a cycle, when CKE, ADV are driven to low and all three chip enables(CS1, CS2, CS2)
are active .
Output Enable(OE) can be used to disable the output at any given time.
Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the
address register, CKE is driven low, all three chip enables(CS1, CS2, CS2) are active, the write enable input signals WE are driven
high, and ADV driven low.The internal array is read between the first rising edge and the second rising edge of the clock and the data
is latched in the output register. At the second clock edge the data is driven out of the SRAM. Also during read operation OE must
be driven low for the device to drive out the requested data.
Write operation occurs when WE is driven low at the rising edge of the clock. BW[d:a] can be used for byte write operation. The pipe-
lined NtRAMTM uses a late-late write cycle to utilize 100% of the bandwidth.
At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle
later.
Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is
provided by the external address. The burst address counter wraps around to its initial state upon completion.
The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected.
And when this pin is high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At
this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up
time.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
00
11
10
BQ TABLE
LBO PIN
LOW
First Address
Fourth Address
Case 1
A1 A0
00
01
10
11
Case 2
A1 A0
01
10
11
00
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
(Interleaved Burst, LBO=High)
Case 3
A1 A0
10
11
00
01
Case 4
A1 A0
11
10
01
00
(Linear Burst, LBO=Low)
Case 3
A1 A0
10
11
00
01
Case 4
A1 A0
11
00
01
10
www.DataSheet.in
- 5 - May 1999
Rev 3.0

5 Page





KM736V749 arduino
KM736V749
KM718V849
128Kx36 & 256Kx18 Pipelined NtRAMTM
SLEEP MODE
SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SLEEP MODE is dictated by the length of time the ZZ is in a High state.
After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z
The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP
MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend-
ing operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given
while the SRAM is transitioning out of SLEEP MODE.
SLEEP MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during SLEEP MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SLEEP current
ZZ inactive to exit SLEEP current
CONDITIONS
ZZ VIH
SYMBOL
ISB2
tPDS
tPUS
tZZI
tRZZI
MIN
2
2
0
MAX
10
2
UNITS
mA
cycle
cycle
cycle
SLEEP MODE WAVEFORM
K
ZZ
Isupply
All inputs
(except ZZ)
tPDS
ZZ setup cycle
tZZI
ISB2
Deselect or Read Only
Outputs
(Q)
High-Z
tPUS
ZZ recovery cycle
tRZZI
Deselect or Read Only
Normal
operation
cycle
DONT CARE
www.DataSheet.in
- 11 -
May 1999
Rev 3.0

11 Page







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