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PDF W78L051A Data sheet ( Hoja de datos )
| Número de pieza | W78L051A | |
| Descripción | 8-BIT MICROCONTROLLER | |
| Fabricantes | Winbond | |
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W78LE51/W78L051A
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 2
2. FEATURES ................................................................................................................................. 2
3. PIN CONFIGURATIONS ............................................................................................................ 3
4. PIN DESCRIPTION..................................................................................................................... 4
5. FUNCTIONAL DESCRIPTION ................................................................................................... 5
6. ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 10
7. SECURITY BITS ....................................................................................................................... 12
8. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 13
9. DC CHARACTERISTICS.......................................................................................................... 14
10. AC CHARACTERISTICS .......................................................................................................... 16
11. TIMING WAVEFORMS ............................................................................................................. 18
12. TYPICAL APPLICATION CIRCUITS ........................................................................................ 21
13. PACKAGE DIMENSIONS ......................................................................................................... 23
14. REVISION HISTORY ................................................................................................................ 25
www.DataSheet.in
Publication Release Date: November 6, 2006
- 1 - Revision A6
1 page  
W78LE51/W78L051A
5. FUNCTIONAL DESCRIPTION
The W78L051 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt informations:
INTERRUPT SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
0 (highest)
1
2
3
4
5
6 (lowest)
ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
XICON.2
XICON.6
INTERRUPT TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
XICON.0
XICON.3
www.DataSheet.in
Publication Release Date: November 6, 2006
- 5 - Revision A6
5 Page 
W78LE51/W78L051A
P3.0 P3.1 P3.2 P3.3
OPERATIONS (A9 (A13 (A14 (OE
CTRL) CTRL) CTRL) CTRL)
P3.6
( CE )
P3.7
( OE )
EA
(VPP)
P2, P1
(A15..A0)
P0
(D7..D0)
NOTE
Read
0 0 0 0 0 0 1 Address Data Out
Output Disable 0 0 0 0 0 1 1 X Hi-Z
Program
0 0 0 0 0 1 VCP Address Data In
Program Verify 0 0 0 0 1 0 VCP Address Data Out @3
Erase
1
0
0
0
0
1
VEP
A0:0,
others: X
Data In
0FFH
@4
Erase Verify 1 0 0 0 1 0 VEP Address Data Out @5
Program/Erase
Inhibit
X
0
0
0
1
1
VCP/
VEP
X
X
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
www.DataSheet.in
Publication Release Date: November 6, 2006
- 11 -
Revision A6
11 Page | ||
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