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PDF EP5382Q Data sheet ( Hoja de datos )

Número de pieza EP5382Q
Descripción (EP5352Q - EP5382Q) 500/600/800mA Synchronous Buck Regulators
Fabricantes Enpirion 
Logotipo Enpirion Logotipo



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No Preview Available ! EP5382Q Hoja de datos, Descripción, Manual

EP5352Q/EP5362Q/EP5382Q
500/600/800mA Synchronous Buck Regulators
With Integrated Inductor
RoHS Compliant
ENABLE
UVLO
Thermal Limit
Current Limit
Soft Start
(-)
PWM
Comp
(+)
Sawtooth
Generator
VIN
Logic
P-Drive
N-Drive
Compensation
Network
(-)
Error
Amp
(+)
VREF
DAC
Switch
VOUT
GND
VSENSE
VFB
Voltage
Select
Package Boundry
VS0 VS1 VS2
Product Highlights
Revolutionary integrated inductor
Very small solution foot print*
Fully RoHS compliant; MSL 3 260°C reflow
Only two low cost components required
5mm x 4mm x1.1mm QFN package
Wide 2.4V to 5.5V input range
500, 600, 800 mA output current versions
Less than 1 μA standby current
4 MHz switching frequency
Fast transient response
Very low ripple voltage; 5mVp-p typical
3 Pin VID Output Voltage select
External divider option
Dynamically adjustable output
Designed for Low noise/EMI
Short circuit, UVLO, and thermal protection
Product Overview
The Ultra-Low-Profile EP53X2Q product family is
targeted to applications where board area and
profile are critical. EP53X2Q is a complete power
conversion solution requiring only two low cost
ceramic MLCC caps. Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EP53x2Q family is engineered to simplify design
and to minimize layout constraints. High
switching frequency and internal type III
compensation provides superior transient
response. With a 1.1 mm profile, the EP53x2 is
perfect for space and height limited applications.
A 3-pin VID output voltage select scheme
provides seven pre-programmed output voltages
along with an option for external resistor divider.
Output voltage can be programmed on-the-fly to
provide fast, dynamic voltage scaling.
Typical Application Circuit
VIN
2.2uF
Voltage
Select
ENABLE
Vin
VSense
Vout
VS0 VFB
VS1
VS2 GND
VOUT
10μF
Figure 1. Typical application circuit.
Applications
Area constrained applications
Mobile multimedia, smartphone & PDA
Mobile and Cellular platforms
VoIP and Video phones
Personal Media Players
FPGA, DSP, IO & Peripherals
*Optimized PCB layout Gerber files downloadable from the Enpirion website to assure first pass design success.
www.Dat0a3S1h32eet.in
4/28/2009
Rev:B

1 page




EP5382Q pdf
Functional Block Diagram
EP5382Q/EP5362Q/EP5352Q
VIN
ENABLE
UVLO
Thermal Limit
Current Limit
Soft Start
(-)
PWM
Comp
(+)
Sawtooth
Generator
Figure 4. Functional block diagram.
Logic
P-Drive
N-Drive
Compensation
Network
(-)
Error
Amp
(+)
VREF
DAC
Switch
VOUT
GND
VSENSE
VFB
Voltage
Select
Package Boundry
VS0 VS1 VS2
©Enpirion 2009 all rights reserved, E&OE
www.Dat0a3S1h32eet.in
5
4/28/2009
www.enpirion.com
Rev:B

5 Page





EP5382Q arduino
EP5382Q/EP5362Q/EP5352Q
VS2
VS1
VS0
ENABLE
17
18
19
20
10 NC
9 NC
8 NC
7 VOUT
VIN
4.7uF/2.2uF
(see layout recommendation 3)
10μF
VOUT
Figure 6. Example application, Vout=1.2V.
Figure 7 shows an example schematic using an external voltage divider. VS0=VS1=VS2= “1”. The
resistor values are chosen to give an output voltage of 2.6V.
VS2
VS1
VS0
ENABLE
17
18
19
20
10 NC
9 NC
8 NC
7 VOUT
Rb=60K
Ra=200K
VIN
4.7uF
(see layout recommendation 3)
10μF
VOUT
Figure 7. Schematic showing the use of external divider option, Vout = 2.6V.
Figure 8 shows two example board layouts. Note the placement of the input and output capacitors.
They are placed close to the device to minimize the physical area of the AC current loops. Note the
placement of the vias per recommendation 3.
©Enpirion 2009 all rights reserved, E&OE
www.Dat0a3S1h32eet.in
11
4/28/2009
www.enpirion.com
Rev:B

11 Page







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