PDF IDTCV193 Data sheet ( Hoja de datos )

Número de pieza	IDTCV193
Descripción	PROGRAMMABLE FLEXPC LP/S CLOCK
Fabricantes	Integrated Device Technology
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No Preview Available ! IDTCV193 PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR COMMERCIALTEMPERATURERANGE PROGRAMMABLE FLEXPC LP/S CLOCK FOR INTEL BASED SYSTEMS IDTCV193 ADVANCE INFORMATION FEATURES: • Compliant with Intel CK505 Gen II spec • One high precision PLL for CPU, SSC and N programming • One high precision PLL for SRC, SSC and N programming • One high precision PLL for SATA/PCI, and SSC • One high precision PLL for 96MHz/48MHz • Push-pull IOs for differential outputs • Support spread spectrum modulation, –0.5 down spread and others • Support SMBus block read/write, byte read/write • Available in TSSOP package KEY FEATURES • Direct CPU and SRC clock frequency programming—write the Hex number into Byte [16:18], 1MHz stepping. • Linear and smooth transition for the CPU and SRC frequency programming. • SATA PLL source hardware select latch pin, PLL2 or PLL4. • Internal serial resistor hardware enable latch pin. • WOL 25MHz support. OUTPUTS: • 2 - 0.7V differential CPU CLK pair • 10 - 0.7V differential SRC CLK pair • 1 - CPU_ITP/SRC differential clock pair • 1 - SRC0/DOT96 differential clock pair • 6 - PCI, 33.3MHz • 1 - 48MHz • 1 - REF • 1 - SATA KEY SPECIFICATIONS: • CPU/SRC CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 500ps • All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II phase noise requirement. • SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal interpair skew = 0 ps FUNCTIONAL BLOCK DIAGRAM XTAL_IN XTAL_OUT SDATA SCLK XTAL Osc Amp SM Bus Controller CKPWRGD/PD# CPU_STOP# PCI_STOP# SRC5_EN ITP_EN CR_[H:A]# FSC,B,A SATA_SEL SR_ENABLE Control Logic PLL1 SSC N Programmable PLL3 SSC PLL4 SSC N Programmable Fixed PLL PLL2 CPU Output Buffer Stop Logic PCI/SATA SRC CLK Output Buffer Stop Logic SRC CLK Output Buffer Stop Logic 48MHz/96MHz Output BUffer REF CPU[1:0] CPU_ITP/SRC8 SRC1/25MHz/24.576MHz PCI[4:0], PCIF5 SATA/SRC2 SRC[7:3], [11:9] 48MHz DOT96/SRC0 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE © 2005 Integrated Device Technology, Inc. www.DataSheet.in IDT CONFIDENTIAL 1 APRIL 8, 2009 DSC 7165 1 page IDTCV193 PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR COMMERCIALTEMPERATURERANGE SEL_SRC1_25_24.576 (PIN 48) VOLTAGE DECODING TABLE state Low Mid High Min 0V 1.3V 2.4V Typ 0.55V 1.65V 2.75V Max 0.9V 2V VDD SR_ENABLE TABLE SR_ENABLE 0 Need external 33 ohm serial resistor, Byte19 bit7 = 0 1 (default) Enable 33 ohm internal serial resistor, Byte19 bit7 = 1 SEL_SRC1_25_24.576 FUNCTION TABLE Sel_SRC1_25_24.576 (pin48 ) Low CPU PLL1 PCI PLL4 Pin 17 25MHz, PLL3 (SS off) Mid PLL1 PLL4 SRCT1 Pin 18 25MHz PLL3 (SS off) SRCC1 SRC 48/96 PLL4 down PLL2, fixed PLL4 down PLL2, fixed High SATA_SEL TABLE SATA_SEL 0 1 PLL1 PLL4 25MHz PLL2 24.576MHz PLL4 down PLL2, fixed PLL3 (SS off) SRC2/SATA PLL4 (SRC PLL, SSC) PLL2 (48/96 PLL) DEVICE ID TABLE ID3,ID2,ID1,ID0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CK505 56 pin TSSOP CK505 64 pin TSSOP 48 pin QFN 56 pin QFN 64 pin QFN 72 pin QFN 48 pin SSOP 56 pin SSOP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Comments CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 YC CK505 Derivative (non YC) IO_VOUT [2:0] TABLE 000 001 010 011 100 101 110 111 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1V IDT CONFIDENTIAL 5 www.DataSheet.in 5 Page IDTCV193 PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR COMMERCIALTEMPERATURERANGE BYTE 15, WATCH DOG(1) Bit Output(s) Affected Description / Function 0 1 7 Watch Dog Enable Watch Dog Alarm Enable Disabled Enabled 6 Watch Dog Select Watch Dog Hard/Soft Alarm Select Hard Alarm Only Hard and Soft Alarm 5 Watch Dog Hard Alarm Status Watch Dog Hard Alarm Status Normal Alarm 4 Watch Dog Soft Alarm Status Watch Dog Soft Alarm Status Normal Alarm 3 Watch Dog control Watch Dog Time Base Control 290ms base 1160ms base 2 WD_1_ Timer 2 WatchDog_1_Alarm Timer 1 WD_1_ Timer 1 Default is 7*290ms 0 WD_1_ Timer 0 NOTE: 1. Hard Alarm switch to HW FS frequency. Type RW RW R R RW RW RW RW Power On 0 0 0 1 1 1 BYTE 16 Bit Output(s) Affected Description / Function Set Byte15 bit7 = 1 after Power Down 7 WDEAPD to enable the watch dog after the power down 6 Reserved 5 Reserved 4 Test _scl N programming 3 Enable 2 Reserved 1 Reserved 0 CPUN8 On chip test mode enable 0 1 Type Power On Disabled normal Disabled Enabled SCLK=1, clk outputs = 1 SCLK=0, clk outputs=0 RW RW RW RW Enabled RW RW RW RW 0 0 0 0 0 0 0 FS latch BYTE 17 (PLL1) Bit Output(s) Affected 7 CPUN7 6 CPUN6 5 CPUN5 4 CPUN4 3 CPUN3 2 CPUN2 1 CPUN1 0 CPUN0 Description / Function CPU clock frequency = CPUN [8:0] (Hex) 0 1 Type Power On RW RW RW RW FS latch RW RW RW RW www.DataSheet.in IDT CONFIDENTIAL 11 11 Page

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