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PDF FS714X Data sheet ( Hoja de datos )
| Número de pieza | FS714X | |
| Descripción | Programmable Phase-Locked Loop Clock Generator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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FS714x
Programmable Phase-Locked Loop Clock Generator
1.0 Key Features
• Extremely flexible and low-jitter phase locked loop (PLL) frequency synthesis
• No external loop filter components needed
• 150MHz CMOS or 340MHz PECL outputs
• Completely configurable via I2C™-bus
• Up to four FS714x can be used on a single I2C-bus
• 3.3V operation
• Independent on-chip crystal oscillator and external reference input
• Very low “cumulative” jitter
2.0 Description
The FS714x (FS7140x or FS7145x) is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component
count in a variety of electronic systems. Via the I2C-bus interface, the FS714x can be adapted to many clock generation requirements.
The length of the reference and feedback dividers, their fine granularity and the flexibility of the post divider make the FS714x the most
flexible stand-alone PLL clock generator available.
Figure 1: Pin Configuration: 16-pin (0.150") SOIC, 16-pin (5.3mm) SSOP
3.0 Applications
• Precision frequency synthesis
• Low-frequency clock multiplication
• Video line-locked clock generation
• Laser beam printers (FS7145)
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 5
www.DataSheet.in
Publication Order Number:
FS714x/D
1 page  
FS714x
When not using the REF input, it is preferred to leave it floating or connected to VDD.
4.1.6. Feedback Divider Source MUX
The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by
the FBKDSRC bit.
Ordinarily, for frequency synthesis, the output of the VCO is used. Use the output of the post divider only where a deterministic phase
relationship between the output clock and reference clock are desired (line-locked mode, for example).
4.1.7. Device Shutdown
Two bits are provided to effect shutdown of the device if desired, when it is not active. SHUT1 disables most externally observable
device functions. SHUT2 reduces device quiescent current to absolute minimum values. Normally, both bits should be set or cleared
together.
Serial communications capability is not disabled by either SHUT1 or SHUT2.
4.2 Differential Output Stage
The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the
programming registers.
If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink
current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of output
sink current to IPRG current is 13:1. Source current for the CLKx pins is provided by the pull-up resistors that are part of the Thévenin
termination.
4.2.1. Example
Assume that it is desired to connect a PECL-type fanout buffer right next to the FS7140.
Further assume:
• VDD = 3.3V
• Desired VHI = 2.4V
• Desired VLO = 1.6V
• Equivalent RLOAD = 75 ohms
www.DataSheet.in
Rev. 5 | Page 5 of 19 | www.onsemi.com
5 Page 
FS714x
6.0 Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written.
Table 3: FS7140 Register Map
Address
Byte 7
BIT 7
Reserved
(Bit 63)
BIT 6
Reserved
(Bit 62)
BIT 5
Reserved
(Bit 61)
BIT 4
Reserved
(Bit 60)
BIT 3
Reserved
(Bit 59)
BIT 2
Reserved
(Bit 58)
BIT 1
Reserved
(Bit 57)
BIT 0
Reserved
(Bit 56)
Must be set to “0”
Reserved
Must be set to “0”
Reserved
Must be set to “0”
SHUT2
Must be set to “0”
Reserved
Must be set to “0”
Reserved
Must be set to “0”
Reserved
Must be set to “0”
Reserved
Must be set to “0”
Reserved
Byte 6
Byte 5
(Bit 55)
Must be set to “0”
Reserved
(Bit 47)
Must be set to “0”
CMOS
(Bit 54)
Must be set to “0”
LC
(Bit 46)
Loop filter cap
select
FBKDSRC
(Bit 53)
(Bit 52)
0 = Normal
Must be set to “0”
1 = Powered down
LR[1]
LR[0]
(Bit 45)
(Bit 44)
Loop filter resistor select
FBKDIV[13]
FBKDIV[12]
(Bit 51)
Must be set to “0”
Reserved
(Bit 43)
Must be set to “0”
FBKDIV[11]
(Bit 50)
Must be set to “0”
Reserved
(Bit 42)
Must be set to “0”
FBKDIV[10]
(Bit 49)
Must be set to “0”
(Bit 48)
Must be set to “0”
CP[1]
CP[0]
(Bit 41)
(Bit 40)
Charge pump current select
FBKDIV[9]
FBKDIV[8]
(Bit 39)
(Bit 38)
(Bit 37)
(Bit 36)
(Bit 35)
(Bit 34)
(Bit 33)
(Bit 32)
Byte 4
0 = PECL
1 = CMOS
0 = VCO output
1 = Post divider
output
8192
4096
2048
1024
See Section 4.1.2 for disallowed FBKDIV values
512
256
Byte 3
Byte 2
FBKDIV[7]
(Bit 31)
128
POST2[3]
(Bit 23)
FBKDIV[6]
(Bit 30)
64
POST2[2]
(Bit 22)
FBKDIV[5]
(Bit 29)
32
POST2[1]
(Bit 21)
FBKDIV[4]
FBKDIV[3]
(Bit 28)
(Bit 27)
16 8
See Section 4.1.2 for disallowed FBKDIV values
POST2[0]
POST1[3]
(Bit 20)
(Bit 19)
FBKDIV[2]
(Bit 26)
4
POST1[2]
(Bit 18)
FBKDIV[1]
(Bit 25)
2
POST1[1]
(Bit 17)
FBKDIV[0]
(Bit 24)
1
POST1[0]
(Bit 16)
Byte 1
Byte 0
Modulus = N +1 (N = 0 to 11); See Table 8
POST3[1]
POST3[0]
SHUT1
(Bit 15)
(Bit 14)
(Bit 13)
Modulus = 1,2,4, or 8; See Table 8
0 = Normal
1 = Powered down
REFDIV[7]
(Bit 7)
REFDIV[6]
(Bit 6)
REFDIV[5]
(Bit 5)
REFDSRC
(Bit 12)
0 = Crystal
oscillator
1 = REF pin
REFDIV[4]
(Bit 4)
REFDIV[11]
(Bit 11)
2048
REFDIV[3]
(Bit 3)
Modulus = N +1 (N = 0 to 11); See Table 8
REFDIV[10]
REFDIV[9]
REFDIV[8]
(Bit 10)
(Bit 9)
(Bit 8)
1024 512 256
REFDIV[2]
(Bit 2)
REFDIV[1]
(Bit 1)
REFDIV[0]
(Bit 0)
128 64 32 16 8 4 2 1
www.DataSheet.in
Rev. 5 | Page 11 of 19 | www.onsemi.com
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet FS714X.PDF ] | |
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