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PDF DAC1008D750 Data sheet ( Hoja de datos )

Número de pieza DAC1008D750
Descripción Dual 10-bit DAC up to 750 Msps
Fabricantes NXP Semiconductors 
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DAC1008D750
Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
with JESD204A interface
Rev. 01 — 4 October 2010
Objective data sheet
1. General description
The DAC1008D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1008D750 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1008D750 also includes a 2×, 4× or 8× clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1008D750 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
„ Dual 10-bit resolution
„ 750 Msps maximum update rate
„ Selectable 2×, 4× or 8× interpolation
filters
„ Input data rate up to 312.5 Msps
„ Very low-noise cap-free integrated PLL
„ 32-bit programmable NCO frequency
„ Four JESD204A serial input lanes
„ 1.8 V and 3.3 V power supplies
„ LVDS compatible clock inputs
„ IMD3: 76 dBc; fs = 737.28 Msps;
fo = 140 MHz
„ ACPR: 64 dBc; two carriers WCDMA;
fs = 737.28 Msps; fo = 153.6 MHz
„ Typical 1.26 W power dissipation at 4×
interpolation, PLL off and 740 Msps
„ Power-down mode and Sleep modes
„ Differential scalable output current from
1.6 mA to 22 mA
„ On-chip 1.25 V reference
„ External analog offset control
(10-bit auxiliary DACs)
„ Internal digital offset control
„ Inverse (sin x) / x function
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DAC1008D750 pdf
NXP Semiconductors
DAC1008D750
2×, 4× or 8× interpolating with JESD204A
DAC1008D750_1
Objective data sheet
Table 2. Pin description …continued
Symbol
Pin Type[1] Description
AGND
12 G
analog ground
AUXBN
13 O
complementary auxiliary DAC B output
AUXBP
14 O
auxiliary DAC B output
VDDA(3V3)
AGND
15 P
16 G
analog supply voltage 3.3 V
analog ground
VDDA(1V8)
AGND
17 P
18 G
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
19 P
20 P
21 G
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
IOUTBN
22 O
complementary DAC B output current
IOUTBP
23 O
DAC B output current
AGND
24 G
analog ground
AGND
25 G
analog ground
IOUTAP
26 O
DAC A output current
IOUTAN
27 O
complementary DAC A output current
AGND
28 G
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
29 P
30 P
31 G
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
VDDA(1V8)
AGND
32 P
33 G
analog supply voltage 1.8 V
analog ground
VDDA(3V3)
AUXAP
34 P
35 O
analog supply voltage 3.3 V
auxiliary DAC A output current
AUXAN
36 O
complementary auxiliary DAC A output current
AGND
37 G
analog ground
VDDA(1V8)
VDDA(1V8)
AGND
38 P
39 P
40 G
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
CLKINP
41 I
clock input
CLKINN
42 I
complementary clock input
AGND
43 G
analog ground
VDDA(1V8)
MDS_P
44 P
45 I/O
analog supply voltage 1.8 V
multi-device synchronization
MDS_N
46 I/O
complementary multi-device synchronization
VDDD(1V8)
n.c.
47 P
48 -
digital supply voltage 1.8 V
not connected
VDDD(1V8)
SYNC_OUTN
49 P
50 O
digital supply voltage 1.8 V
synchronization request to transmitter, complementary
output
SYNC_OUTP
51 O
synchronization request to transmitter
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 4 October 2010
© NXP B.V. 2010. All rights reserved.
5 of 99
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DAC1008D750 arduino
NXP Semiconductors
DAC1008D750
2×, 4× or 8× interpolating with JESD204A
Table 5. Characteristics …continued
VDDA(1V8) = VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND and GND are shorted together; Tamb = 40 °C to +85 °C;
typical values measured at VDDA(1V8) = VDDD = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum
sample rate; PLL off unless otherwise specified.
Symbol
Parameter
Conditions
Test[1] Min Typ Max
Unit
ACPR
adjacent channel
power ratio
NCO on; interpolation;
fs = 737.28 Msps; fo = 96
MHz
1 carrier; BW = 5 MHz
C
- 67 -
dBc
2 carriers; BW = 10 MHz
C
- 64 -
dBc
4 carriers; BW = 20 MHz
C
- 60 -
dBc
NCO on; 4× interpolation;
fs = 737.28 Msps; fo = 153.6
MHz
1 carrier; BW = 5 MHz
C
- 67 -
dBc
2 carriers; BW = 10 MHz
C
- 64 -
dBc
4 carriers; BW = 20 MHz
C
- 59 -
dBc
NSD
noise spectral density fs = 737.28 Msps;
4× interpolation;
fo = 153.6 MHz at 0 dBFS
I
- 145 -
dBm/Hz
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] Delay between the deassertion of bits FORCE_RESET_FCLK and FORCE_RESET_DCLK and the deassertion of the sync signal. It
reflects the delay required by DAC1008D750 to lock to a JESD204A stream. It supposes that the TX is already transmitting
K28.5 characters in error-free conditions.
[3] CLKINP/CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 Ω and 120 Ω (see
Figure 16) should be connected across the pins.
[4] |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
and the inductance between the receiver and the driver circuit ground voltage.
[5] Vin_p and Vin_n inputs are differential CML inputs. They are terminated internally to Vtt via 50 Ω (see Figure 4).
[6] SYNC_OUTP/SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 Ω
and 120 Ω.
[7] IMD3 rejection with 6 dBFS/tone.
DAC1008D750_1
Objective data sheet
www.DataSheet.in
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 4 October 2010
© NXP B.V. 2010. All rights reserved.
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