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PDF TDA19978A Data sheet ( Hoja de datos )

Número de pieza TDA19978A
Descripción Quad HDMI 1.3a receiver interface
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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TDA19978A
Quad HDMI 1.3a receiver interface with equalizer (HDTV up to
1080p, up to UXGA for PC formats)
Rev. 03 — 16 April 2010
Product data sheet
1. General description
The TDA19978A is a four input HDMI 1.3a compliant receiver with embedded EDID
memory. The built in auto-adaptive equalizer improves signal quality and allows the use of
cable lengths up to 25 m (laboratory tested with a 0.5 mm (24 AWG) cable at
2.05 gigasamples per second). The HDCP key set is stored in non-volatile One Time
Programmable (OTP) memory for maximum security. In addition, the TDA19978A is
delivered with software drivers to ease configuration and use.
The TDA19978A supports:
TV resolutions:
480i (1440 × 480i at 60 Hz), 576i (1440 × 576i at 50 Hz) to HDTV (up to
1920 × 1080p at 50/60 Hz)
WUXGA (1920 × 1200p at 60 Hz) reduced blanking format
PC resolutions:
VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz)
Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock)
Gamut boundary description
IEC 60958/IEC 61937, One Bit Audio (in SACD), DST (in compressed DSD) and HBR
stream
The TDA19978A includes:
An enhanced PC and TV format recognition system
Generation of a 128/256/512 × fs system clock allowing the use of simple audio DACs
without an integrated PLL (such as the UDA1334BTS)
An embedded oscillator (an external crystal can also be used)
Improved audio clock generation using an external reference clock
One Bit Audio (in SACD), DST (in compressed DSD) and HBR stream support
The TDA19978A converts HDMI streams with or without HDCP into RGB or YCbCr digital
signals. The YCbCr digital output signal can be 4:4:4 or 4:2:2 semi-planar format based
on the ITU-R BT.601 standard or 4:2:2 based on the ITU-R BT.656 format. The device can
adjust the output timing of the video port by altering the values for tsu(Q) and th(Q). In
addition, all settings are controllable using the I2C-bus.
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TDA19978A pdf
NXP Semiconductors
7. Pinning information
7.1 Pinning
TDA19978A
Quad HDMI 1.3a receiver with digital processing
1 108
36 TDA19978AHV 73
Fig 2. Pin configuration (HLQFP144)
001aah367
7.2 Pin description
Table 3. Pin description
Symbol
Pin
VSSC
PD
1
2
VDDH(3V3)
RXDC+
3
4
RXDC
5
VSSH
RXCC
6
7
RXCC+
8
VDDH(3V3)
RXD0+
9
10
RXD0
11
VSSH
RXC0
12
13
RXC0+
14
VDDH(1V8)
RXD1+
15
16
RXD1
17
VSSH
RXC1
18
19
RXC1+
20
VDDH(3V3)
RXD2+
21
22
RXD2
23
Type[1] Description
G ground for the digital core
I power-down control input (active HIGH)
P HDMI receiver supply voltage; 3.3 V
I HDMI input D positive clock channel
I HDMI input D negative clock channel
G HDMI receiver ground
I HDMI input C negative clock channel
I HDMI input C positive clock channel
P HDMI receiver supply voltage; 3.3 V
I HDMI input D positive data channel 0
I HDMI input D negative data channel 0
G HDMI receiver ground
I HDMI input C negative data channel 0
I HDMI input C positive data channel 0
P HDMI receiver supply voltage; 1.8 V
I HDMI input D positive data channel 1
I HDMI input D negative data channel 1
G HDMI receiver ground
I HDMI input C negative data channel 1
I HDMI input C positive data channel 1
P HDMI receiver supply voltage; 3.3 V
I HDMI input D positive data channel 2
I HDMI input D negative data channel 2
TDA19978A_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 38
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TDA19978A arduino
NXP Semiconductors
TDA19978A
Quad HDMI 1.3a receiver with digital processing
8.10 Packet extraction
Information sent during the Data Island periods are extracted from the HDMI data stream.
Audio clock regeneration, general control and InfoFrames can be read using the I2C-bus
while audio samples are sent to the audio FIFO.
The TDA19978A can receive the new HDMI 1.3a packets, general control and color
gamut metadata info packets.
In audio applications, the TDA19978A manages HBR packets for high bit rate
compressed audio streams (IEC 61937), One Bit Audio samples and DST packets for
One Bit Audio and SACD with DSD and DST audio streams.
The TDA19978A includes a two channel status decoder supporting multi-channel
reception for Audio Sample Packets. This enables the user to obtain channel status
information from the IEC 60958/IEC 61937 stream such as:
The audio stream type (non-linear as IEC 61937 or L-PCM as IEC 60958)
Copyright protection
Sampling frequency
Refer to IEC 60958/IEC 61937 specifications for more details.
An update of each InfoFrame or the channel status content is indicated by a register bit
and the HIGH-to-LOW transition on output pin VAI. This makes CPU polling unnecessary.
8.11 Audio PLL
The TDA19978A generates a 128/256/512 × fs system clock enabling the use of simple
audio DACs without an integrated PLL, such as the UDA1334BTS. The programming of
the audio PLL can be either automatic, using the audio clock regeneration parameters
found in the Data Islands or set manually using the I2C-bus.
All standard audio sampling frequencies 32 kHz, 44.1 kHz, 88.2 kHz, 176.4 kHz, 48 kHz,
96 kHz and 192 kHz are accepted by the device.
8.12 Audio formatter
Audio samples can be output in either S/PDIF, I2S-bus formats or DSD (SACD). In I2S-bus
or S/PDIF modes, up to eight audio channels can be controlled using the audio port pins
(AP0 to AP5). In DSD mode (SACD), up to six audio channels can be controlled using the
these pins. The audio port mapping depends on the channel allocation (see Table 4,
Table 5 and Table 6 for detailed information). In the following tables, all ports are LV-TTL
compatible
TDA19978A_3
Product data sheet
www.DataSheet.in
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 16 April 2010
© NXP B.V. 2010. All rights reserved.
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