|
|
PDF TDA19977B Data sheet ( Hoja de datos )
| Número de pieza | TDA19977B | |
| Descripción | Triple input HDMI 1.4a compliant receiver interface | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TDA19977B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
TDA19977A; TDA19977B
Triple input HDMI 1.4a compliant receiver interface with
equalizer (up to 1080p for HDTV, and UXGA for PC formats
Rev. 3 — 19 November 2010
Product data sheet
1. General description
The TDA19977A; TDA19977B is a three input HDMI 1.4a compliant receiver with
embedded EDID memory. The built-in auto-adaptive equalizer, improves signal quality
and allows the use of cable lengths of up to 25 m which are laboratory tested with a
0.5 mm (24 AWG) cable at 2.05 gigasamples per second. The HDCP (TDA19977A only)
key set is stored in non-volatile OTP (One Time Programmable) memory for maximum
security. In addition, the TDA19977A; TDA19977B is delivered with software drivers to
ease configuration and use.
The TDA19977A; TDA19977B supports:
• TV resolutions:
– 480i (1440 × 480i at 60 Hz), 576i (1440 × 576i at 50 Hz) to HDTV (up to
1920 × 1080p at 50/60 Hz)
– WUXGA (1920 × 1200p at 60 Hz) reduced blanking format
• PC resolutions:
– VGA (640 × 480p at 60 Hz) to UXGA (1600 × 1200p at 60 Hz)
• Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock)
• Gamut boundary description
• IEC 60958/IEC 61937, OBA (One Bit Audio), DST (Direct Stream Transfer) and HBR
(High Bit Rate) stream
The TDA19977A; TDA19977B includes:
• An enhanced PC and TV format recognition system
• Generation of a 128/256/512 × fs system clock allowing the use of simple audio DACs
without an integrated PLL (such as the UDA1334BTS)
• An embedded oscillator (an external crystal can also be used)
• Improved audio clock generation using an external reference clock
• OBA (as used in SACD), DST and HBR stream support
The TDA19977A; TDA19977B converts HDMI streams with or without HDCP
(TDA19977A only) into RGB or YCbCr digital signals. The YCbCr digital output signal can
be 4:4:4 or 4:2:2 semi-planar format based on the ITU-R BT.601 standard or 4:2:2 based
on the ITU-R BT.656 format. The device can adjust the output timing of the video port by
altering the values of tsu(Q) and th(Q). In addition, all settings are controllable using the
I2C-bus.
www.DataSheet.in
1 page  
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
HDMI A (channels 0/1/2)
HDMI A (channel A)
RRX1
HDMI B (channels 0/1/2)
HDMI B (channel B)
HDMI C (channels 0/1/2)
HDMI C (channel C)
RRX2
XTALIN/MCLK
XTALOUT
TERMINATION
RESISTANCE
CONTROL
TERMINATION
RESISTANCE
CONTROL
TERMINATION
RESISTANCE
CONTROL
CRYSTAL
OSCILLATOR
SYNC
TIMING
MEASUREMENT
I2C-BUS SLAVE
INTERFACE
SDA/SCL
OTP (1)
MEMORY
AUDIO
PLL
AUDIO
FORMATTER
PACKET
EXTRACTION
AUDIO
FIFO
AP4/WS
AP0 to AP3
ACLK
SYSCLK/AP5
EQUALIZER
HDMI
RECEIVER
AND
HDCP
COLOR
DEPTH
UNPACKING
VIDEO
OUTPUT
FORMATTER
VP[29:0]
VCLK
EDID
MEMORY
TDA19977
POWER
MANAGEMENT
VHREF
TIMING
GENERATOR
DE
HS/HREF
VS/VREF
CS/FREF
HSDAA/ HSDAB/ HSDAC/
HSCLA HSCLB HSCLC
001aai381
(1) only used by TDA19977A.
Fig 1. Block diagram of TDA19977A; TDA19977B
5 Page 
NXP Semiconductors
TDA19977A; TDA19977B
Triple input HDMI receiver interface with digital processing
8.4 Equalizer
The auto-adaptive equalizer automatically measures and selects the settings which
provide the best signal quality for each cable. This improves signal quality and enables
the use of cable lengths up to 25 m (laboratory tested, contact NXP for detailed
information). The equalizer is fully automatic and consequently does not need any
external control.
8.5 Activity detection
The TDA19977A; TDA19977B uses activity detection to automatically select the active
HDMI input. An internal, fully programmable, frequency filter controls activity detection. It
sees only the activity on the HDMI inputs with a frequency range between fmin (22.5 MHz)
and fmax (205 MHz).
This activity detection can generate an interrupt enabling users to manage each HDMI
input.
8.6 High-bandwidth digital content protection (TDA19977A only)
The HDMI receiver also contains the HDCP decryption function. The keys provided by the
OTP non-volatile memory in encrypted format are decrypted and then stored in the HDCP
module. This is particularly suitable for repeater applications. The TDA19977A manages
all HDCP repeater functions based on the HDCP 1.4 specification.
Three DDC-buses HSCLA/HSDAA; HSCLB/HSDAB and HSCLC/HSDAC are integrated
into the HDCP function, one bus for each HDMI input. The DDC-bus connected to the
HDCP block is automatically selected based on the active HDMI input. The unused inputs
are disconnected from the DDC-bus (no acknowledge). No additional CPU processing is
required because the authentication phase and the re-key calculation are fully managed
by the TDA19977A.
8.7 Color depth unpacking
In Deep Color mode, the TDA19977A; TDA19977B receives several fragments of a pixel
group at the HDMI link frequency. This block translates the received pixel group into pixels
at the pixel frequency. This operation is fully automatic and does not need any external
control.
8.8 Derepeater
The HDMI source uses pixel repetition to increase the transmitted pixel clock for
transmitting video formats at native pixel rates below 25 Mpixel/s or to increase the
number of audio sample packets in each line. The derepeater function discards repeated
pixels and divides the clock to reproduce the native video format.
8.9 Upsample
The HDMI source can use YCbCr 4:2:2 pixel encoding which enables the number of bits
allocated per component to be increased up to 12. The upsample function transforms this
12-bit YCbCr 4:2:2 data stream into a 12-bit YCbCr 4:4:4 data stream by repeating or
linearly interpolating the chrominance pixels Cb and Cr.
Upsampling mode is selected using the I2C-bus.
TDA19977A_TDA19977B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 19 November 2010
© NXP B.V. 2010. All rights reserved.
11 of 40
www.DataSheet.in
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA19977B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TDA19977A | Triple input HDMI 1.4a compliant receiver interface | NXP Semiconductors |
| TDA19977B | Triple input HDMI 1.4a compliant receiver interface | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |