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PDF 6417709S Data sheet ( Hoja de datos )
| Número de pieza | 6417709S | |
| Descripción | HD6417709S | |
| Fabricantes | Renesas Technology | |
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Hay una vista previa y un enlace de descarga de 6417709S (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
www.DataSheet.in
1 page  
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are not connected to any of the internal circuitry; they are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of access to undefined or reserved address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
www.DataSheet.in
Rev. 4.0, 03/03, page iii of xxxvi
5 Page 
Contents
Section 1 Overview and Pin Functions..........................................................................
1.1 SH7709S Features .............................................................................................................
1.2 Block Diagram ..................................................................................................................
1.3 Pin Description ..................................................................................................................
1.3.1 Pin Assignment ....................................................................................................
1.3.2 Pin Function .........................................................................................................
1
1
6
7
7
9
Section 2 CPU....................................................................................................................... 19
2.1 Register Configuration ...................................................................................................... 19
2.1.1 Privileged Mode and Banks.................................................................................. 19
2.1.2 General Registers ................................................................................................. 22
2.1.3 System Registers .................................................................................................. 23
2.1.4 Control Registers.................................................................................................. 23
2.2 Data Formats ..................................................................................................................... 25
2.2.1 Data Format in Registers...................................................................................... 25
2.2.2 Data Format in Memory ....................................................................................... 25
2.3 Instruction Features ........................................................................................................... 26
2.3.1 Execution Environment........................................................................................ 26
2.3.2 Addressing Modes................................................................................................ 28
2.3.3 Instruction Formats............................................................................................... 32
2.4 Instruction Set.................................................................................................................... 35
2.4.1 Instruction Set Classified by Function.................................................................. 35
2.4.2 Instruction Code Map........................................................................................... 50
2.5 Processor States and Processor Modes.............................................................................. 53
2.5.1 Processor States.................................................................................................... 53
2.5.2 Processor Modes .................................................................................................. 54
Section 3 Memory Management Unit (MMU)............................................................ 55
3.1 Overview ........................................................................................................................... 55
3.1.1 Features ................................................................................................................ 55
3.1.2 Role of MMU ....................................................................................................... 55
3.1.3 SH7709S MMU.................................................................................................... 58
3.1.4 Register Configuration ......................................................................................... 61
3.2 Register Description .......................................................................................................... 61
3.3 TLB Functions................................................................................................................... 63
3.3.1 Configuration of the TLB..................................................................................... 63
3.3.2 TLB Indexing ....................................................................................................... 65
3.3.3 TLB Address Comparison.................................................................................... 66
3.3.4 Page Management Information ............................................................................ 68
www.DataSheet.in
Rev. 4.0, 03/03, page ix of xxxvi
11 Page | ||
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| PDF Descargar | [ Datasheet 6417709S.PDF ] | |
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