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PDF QLX4300-S45 Datasheet ( Hoja de datos )

Número de pieza QLX4300-S45
Descripción Quad Lane Extender
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo

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QLX4300-S45 Hoja de datos, Descripción, Manual
Quad Lane Extender
QLx4300-S45
The QLx4300-S45 is a settable quad receive-side
equalizer with extended functionality for advanced
protocols operating with line rates up to 3.125Gb/s such
as InfiniBand (SDR) and 10GBase-CX4. The
QLx4300-S45 compensates for the frequency dependent
attenuation of copper twin-axial cables, extending the
signal reach up to 40m on 24AWG cable.
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the QLx4300-S45 can each be set
to one of 32 compensation levels, providing optimal
signal fidelity for a given media and length. The
compensation level for each filter can be set by either (a)
three external control pins or (b) a serial bus interface.
When the external control pins are used, 18 of the 32
boost levels are available for each channel. If the serial
bus is used, all 32 compensation levels are available.
Operating on a single 1.2V power supply, the
QLx4300-S45 enables per channel throughputs of up to
3.125Gb/s while supporting the lower data rates of
2.5Gb/s and 1.5Gb/s. The QLx4300-S45 uses current
mode logic (CML) inputs/outputs and is packaged in a
4mmx7mm 46 lead QFN. Individual lane impedance
select support is included for module applications.
Features
• Supports data rates up to 3.125Gb/s
• Low power (78mW per channel)
• Low latency (<500ps)
• Four equalizers in a 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Each equalizer boost is independently pin selectable
and programmable
• Beacon signal support and line silence preservation
• 1.2V supply voltage
• Individual channel power-down (impedance select)
Applications
• InfiniBand (SDR)
• 10GBase-CX4
• PCI Express (Gen 1)
• DisplayPort
• XAUI
• SAS (1.0)
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
Typical Application Circuit
QLX4300-S45
QLX4300-S45
<40M 24AWG
November 19, 2009
FN6982.1
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1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page

QLX4300-S45 pdf
QLx4300-S45
Absolute Maximum Ratings
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V
Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJc (°C/W)
46 Ld QFN Package (Note 1). . . . .
32
2.3
Operating Ambient Temperature Range. . . . . . 0°C to +70°C
Storage Ambient Temperature Range . . . . . -55°C to +150°C
Maximum Junction Temperature. . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
Operating Conditions
PARAMETER
Supply Voltage
Operating Ambient Temperature
Bit Rate
SYMBOL
CONDITION
VDD
TA
NRZ data applied to any channel
MIN
1.1
0
1.5
TYP
1.2
25
MAX
1.3
70
3.125
UNITS
V
°C
Gb/s
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS NOTES
Input ‘LOW’ Logic Level
Input ‘HIGH’ Logic Level
Output ‘LOW’ Logic Level
Output ‘HIGH’ Logic Level
‘LOW’ Resistance State
VIL
VIH
VOL
VOH
DI, Clk, ENB
DI, Clk, ENB
IS[k], DO
IS[k], DO
CP[k][A,B,C]
0
750
0
1000
0
0
0
350
VDD
250
VDD
1
mV
mV
mV
mV
kΩ
2
‘MID’ Resistance State
CP[k][B,C]
22.5 25 27.5 kΩ
2
‘HIGH’ Resistance State
CP[k][A,B,C]
500 kΩ 2
Input Current
Current draw on digital pin, i.e.,
CP[k][A,B,C], DI, Clk, ENB
30 100 µA
NOTE:
2. If four CP pins are tied together, the resistance values in this table should be divided by four.
Electrical Specifications Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETERS
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Supply Current
Cable Input Amplitude
Range
IDD
VIN Measured differentially at data source
before encountering channel loss
800
260
1200
1600
mA
mVP-P
3
DC Differential Input
Resistance
Measured on input channel IN[k]
80 100 120
Ω
DC Single-Ended Input
Resistance
Measured on input channel IN[k]P or
IN[k]N
40 50 60
Ω
Input Return Loss
(Differential)
SDD11 50MHz to 3.75GHz
10 dB 4
Input Return Loss
(Common Mode)
SCC11 50MHz to 3.75GHz
6 dB 4
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FN6982.1
November 19, 2009

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QLX4300-S45 arduino
QLx4300-S45
the boost level and one of 18 compensation levels when
the CP[k] pins are used to set the level. The equalizer
transfer functions for a subset of these compensation
levels are plotted in Figure 18. The flexibility of this
adjustable compensation architecture enables signal
fidelity to be optimized on a channel-by-channel basis,
providing support for a wide variety of channel
characteristics and data rates ranging from 2.5Gb/s to
3.125Gb/s. Because the boost level is externally set
rather than internally adapted, the QLx4300-S45
provides reliable communication from the very first bit
transmitted. There is no time needed for adaptation and
control loop convergence. Furthermore, there are no
pathological data patterns that will cause the
QLx4300-S45 to move to an incorrect boost level.
The “Applications Information” section beginning on
page 12 details how to set the boost level by both the
CP-pin voltage approach and the serial programming
approach.
IN[k] P
VDD
50
IN[k] N
50
Buffer
FIGURE 19. CML INPUT EQUIVALENT CIRCUIT FOR THE
QLx4300-S45
VDD
5252
OUT[k] P
OUT[k] N
FIGURE 18. EQUALIZER TRANSFER FUNCTIONS FOR
SETTINGS 0, 5, 10, 15, 20, 25, AND 31 IN
THE QLx4300-S45
CML Input and Output Buffers
The input and output buffers for the high-speed data
channels in the QLx4300-S45 are implemented using
CML. Equivalent input and output circuits are shown in
Figures 19 and 20, respectively.
FIGURE 20. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx4300-S45
NOTE: The load value of 52Ω is used to internally match
SDD22 for a characteristic impedance of 50Ω.
Line Silence/Electrical Idle/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx4300-S45 contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the
fidelity-enhancing benefits of limiting amplification during
active data transmission. Line silence is detected by
measuring the amplitude of the equalized signal and
comparing that to a threshold set by the current at the
DT pin. When the amplitude falls below the threshold,
the output driver stages are muted and held at their
nominal common mode voltage1.
1. The output common mode voltage remains constant during both active data transmission and output muting modes.
11
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