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PDF QLX4300-S45 Datasheet ( Hoja de datos )

Número de pieza QLX4300-S45
Descripción Quad Lane Extender
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo
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QLX4300-S45 datasheet

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QLX4300-S45 pdf
QLx4300-S45
Absolute Maximum Ratings
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V
Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJc (°C/W)
46 Ld QFN Package (Note 1). . . . .
32
2.3
Operating Ambient Temperature Range. . . . . . 0°C to +70°C
Storage Ambient Temperature Range . . . . . -55°C to +150°C
Maximum Junction Temperature. . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
Operating Conditions
PARAMETER
Supply Voltage
Operating Ambient Temperature
Bit Rate
SYMBOL
CONDITION
VDD
TA
NRZ data applied to any channel
MIN
1.1
0
1.5
TYP
1.2
25
MAX
1.3
70
3.125
UNITS
V
°C
Gb/s
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS NOTES
Input ‘LOW’ Logic Level
Input ‘HIGH’ Logic Level
Output ‘LOW’ Logic Level
Output ‘HIGH’ Logic Level
‘LOW’ Resistance State
VIL
VIH
VOL
VOH
DI, Clk, ENB
DI, Clk, ENB
IS[k], DO
IS[k], DO
CP[k][A,B,C]
0
750
0
1000
0
0
0
350
VDD
250
VDD
1
mV
mV
mV
mV
kΩ
2
‘MID’ Resistance State
CP[k][B,C]
22.5 25 27.5 kΩ
2
‘HIGH’ Resistance State
CP[k][A,B,C]
500 kΩ 2
Input Current
Current draw on digital pin, i.e.,
CP[k][A,B,C], DI, Clk, ENB
30 100 µA
NOTE:
2. If four CP pins are tied together, the resistance values in this table should be divided by four.
Electrical Specifications Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETERS
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Supply Current
Cable Input Amplitude
Range
IDD
VIN Measured differentially at data source
before encountering channel loss
800
260
1200
1600
mA
mVP-P
3
DC Differential Input
Resistance
Measured on input channel IN[k]
80 100 120
Ω
DC Single-Ended Input
Resistance
Measured on input channel IN[k]P or
IN[k]N
40 50 60
Ω
Input Return Loss
(Differential)
SDD11 50MHz to 3.75GHz
10 dB 4
Input Return Loss
(Common Mode)
SCC11 50MHz to 3.75GHz
6 dB 4
www.DataSheet.in
5
FN6982.1
November 19, 2009

5 Page

QLX4300-S45 arduino
QLx4300-S45
Typical Performance Characteristics (Continued)
00
-5
Channel 1
-5 Channel 2
-10
Channel 3
-10 Channel 4
-15 -15
-20
-25
Channel 1
Channel 2
-30 Channel 3
Channel 4
-35
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (GHz)
-20
-25
-30
-35
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (GHz)
FIGURE 13. INPUT DIFFERENTIAL RETURN LOSS
FIGURE 14. OUTPUT DIFFERENTIAL RETURN LOSS
FIGURE 15. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNEL
FIGURE 16. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNELS
Operation
The QLx4300-S45 is an advanced quad lane-extender for
high-speed interconnects. A functional diagram of one of
the four channels in the QLx4300-S45 is shown in
Figure 17. In addition to a robust equalization filter to
compensate for channel loss and restore signal fidelity,
the QLx4300-S45 contains unique integrated features to
preserve special signaling protocols typically broken by
other equalizers. The signal detect function is used to
mute the channel output when the equalized signal falls
below the level determined by the Detection Threshold
(DT) pin voltage. This function is intended to preserve
periods of line silence (“quiescent state” in InfiniBand
contexts).
As illustrated in Figure 17, the core of each high-speed
signal path in the QLx4300-S45 is a sophisticated
equalizer followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
IS[k]
IN[k]
SETTABLE
EQUILIZER
LIMITING
AMPLIFIER
OUT[k]
>200kΩ
BIT SELECT
(CP[k]/DI)
AMPLITUDE
DETECTOR
+
-
MUTE
ENABLED
DT
FIGURE 17. FUNCTIONAL DIAGRAM OF A SINGLE
CHANNEL WITHIN THE QLx4300-S45
Individually Adjustable Equalization Boost
Each channel in the QLx4300-S45 features an
independently settable equalizer for custom signal
restoration. Each equalizer can be set to one of 32 levels
of compensation when the serial bus is used to program
10 FN6982.1
November 19, 2009
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