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PDF QLX411GRX Data sheet ( Hoja de datos )

Número de pieza QLX411GRX
Descripción Quad Lane Extender
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! QLX411GRX Hoja de datos, Descripción, Manual

Quad Lane Extender
QLx411GRx
The QLx411GRx is a settable quad receive-side equalizer
with extended functionality for advanced protocols
operating with line rates up to 11.3Gb/s such as
InfiniBand (SDR, DDR and QDR) and 40G Ethernet
(40GBase-CR4). The QLx411GRx compensates for the
frequency dependent attenuation of copper twin-axial
cables, extending the signal reach up to at least 10m on
28AWG cable.
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the QLx411GRx can each be set
to provide optimal signal fidelity for a given media and
length. The compensation level for each filter is set by
two external control pins.
Operating on a single 1.2V power supply, the QLx411GRx
enables per channel throughputs of 10Gb/s to 11.3Gb/s
while supporting lower data rates including 8.5, 6.25, 5,
4.25, 3.125, and 2.5Gb/s. The QLx411GRx uses current
mode logic (CML) inputs/outputs and is packaged in a
4mmx7mm 46 lead QFN. Individual lane LOS support is
included for module applications.
Typical Application Circuit
Features
• Supports data rates up to 11.3Gb/s
• Low power (135mW per channel)
• Low latency (<500ps)
• Four equalizers in a 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Each equalizer boost is independently pin selectable
• Supports 64b/66b encoded data – long run lengths
• Line silence preservation
• 1.2V supply voltage
• Individual lane LOS support
Applications
• QSFP active copper cable modules
• InfiniBand SDR, DDR and QDR
• 40G Ethernet (40GBase-CR4)
• XAUI and RXAUI
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
Tx1[P,N]
Tx2[P,N]
Tx3[P,N]
Tx4[P,N]
Rx1[P,N]
0.1μF
0.1μF
Rx2[P,N]
0.1μF
Rx3[P,N]
0.1μF
Rx4[P,N]
Fabric Switch
1.2V
10nF
4 12
100pF
LOS CP EP VDD
OUT1[P,N]
0.1μF
IN1[P,N]
OUT2[P,N]
0.1μF
IN2[P,N]
QLx411GRx
OUT3[P,N]
0.1μF
IN3[P,N]
OUT4[P,N]
0.1μF
IN4[P,N]
DT 1.2V
Connector Paddle Card
Active Copper Cable Assembly
8-Pair Differential 100
Twin-Axial Cable
10m 28AWG
1.2V
10nF
100pF
12 4
VDD EP CP LOS
0.1μF
IN1[P,N]
OUT1[P,N]
0.1μF
IN2[P,N]
OUT2[P,N]
QLx411GRx
0.1μF
IN3[P,N]
OUT3[P,N]
0.1μF
IN4[P,N]
1.2V
DT
OUT4[P,N]
Connector Paddle Card
Host Channel
Adapter
0.1μF
Rx1[P,N]
0.1μF
Rx2[P,N]
0.1μF
Rx3[P,N]
0.1μF
Rx4[P,N]
Tx1[P,N]
Tx2[P,N]
Tx3[P,N]
Tx4[P,N]
November 19, 2009
FN6989.1
www.DataSheet.in
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




QLX411GRX pdf
QLx411GRx
Electrical Specifications Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 600mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Output Residual Jitter
Output Transition Time
Lane-to-Lane Skew
tr, tf
10Gb/s; Up to 10m 28AWG standard
twin-axial cable (approx. -27dB @ 5GHz);
1200mVP-P VIN 1600mVP-P
20% to 80%
0.25
UI 1, 3, 4
35
50
ps
ps
5
Propagation Delay
From IN[k] to OUT[k]
500 ps
LOS Assert Time
Time to assert Loss-of-Signal (LOS) indicator
when transitioning from active data mode to
line silence mode
50 µs
6
LOS De-Assert Time
Time to de-assert Loss-of-Signal (LOS)
indicator when transitioning from line silence
mode to active data mode
50 µs
6
Data-to-Line Silence
Response Time
Time to transition from active data to line
silence (muted output) on 20m 28AWG
standard twin-axial cable at 5Gb/s
50 µs
6
Line Silence-to-Data
Response Time
Time to transition from line silence mode
(muted output) to active data on 20m 28AWG
standard twin-axial cable at 5Gb/s
50 µs
6
NOTES:
1. After channel loss, differential amplitudes at QLx411GRx inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 4.
2. Temperature = +25°C, VDD = 1.2V.
3. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS.
4. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
5. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
6. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less.
www.DataSheet.in
5
FN6989.1
November 19, 2009

5 Page





QLX411GRX arduino
QLx411GRx
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)
Rev 0, 9/09
6
PIN 1
INDEX AREA
4.00
A
B
39
38
2.80
42X 0.40
6
46 PIN 1
INDEX AREA
1
5.60
5.50 ±0.1
Exp. DAP
(4X) 0.05
TOP VIEW
SIDE VIEW
SEE DETAIL "X"
24
46X 0.20 4
0.10 M C A B
46X 0.40
23
2.50 ±0.1
Exp. DAP
15
16
BOTTOM VIEW
0.70 ±0.05
SIDE VIEW
( 3.80 )
( 2.50)
0.10 C
C
SEATING PLANE
0.05 C
C 0.152 REF 5
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 6.80 )
( 5.50 )
( 42X 0.40)
(46X 0.20)
( 46 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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11
FN6989.1
November 19, 2009

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