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PDF SC16C852V Data sheet ( Hoja de datos )

Número de pieza SC16C852V
Descripción XScale VLIO bus interface
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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SC16C852V
1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared
(IrDA), and XScale VLIO bus interface
Rev. 04 — 14 January 2008
Product data sheet
1. General description
The SC16C852V is a 1.8 V, low power dual channel Universal Asynchronous Receiver
and Transmitter (UART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. SC16C852V can be programmed to operate in extended mode where
additional advanced UART features are available (see Section 6.2). The SC16C852V
family UART provides enhanced UART functions with 128-byte FIFOs, modem control
interface, DMA mode data transfer, and IrDA encoder/decoder. On-board status registers
provide the user with error indications and operational status. System interrupts and
modem control features may be tailored by software to meet specific user requirements.
An internal loopback capability allows on-board diagnostics. Independent programmable
baud rate generators are provided to select transmit and receive baud rates.
The SC16C852V with Intel XScale processor VLIO interface operates at 1.8 V and is
available in HVQFN48 and TFBGA36 packages.
2. Features
I Dual channel high performance UART
I 1.8 V operation
I Advanced packages: HVQFN48 and TFBGA36
I Up to 5 Mbit/s data rate at 1.8 V
I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
I 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
I 128 programmable Receive and Transmit FIFO interrupt trigger levels
I 128 Receive and Transmit FIFO reporting levels (level counters)
I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control
I Programmable Xon/Xoff characters
I 128 programmable hardware and software trigger levels
I Automatic 9-bit mode (RS-485) address detection
I Automatic RS-485 driver turn-around with programmable delay
I Dual channel concurrent write
I UART software reset
I High resolution clock prescaler, from 0 to 15 with granularity of 116 to allow
non-standard UART clock to be used
I Industrial temperature range (40 °C to +85 °C)
I Software compatible with industry standard SC16C652B
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SC16C852V pdf
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
5. Pinning information
5.1 Pinning
terminal 1
index area
AD5 1
AD6 2
AD7 3
RXB 4
RXA 5
TXRDYB 6
TXA 7
TXB 8
OP2B 9
CS 10
n.c. 11
LOWPWR 12
SC16C852VIBS
Transparent top view
Fig 3. Pin configuration for HVQFN48
36 RESET
35 DTRB
34 DTRA
33 RTSA
32 OP2A
31 RXRDYA
30 INTA
29 INTB
28 LLA
27 n.c.
26 n.c.
25 n.c.
002aac351
ball A1
index area
SC16C852VIET
123456
A
B
C
D
E
F
002aac350
Transparent top view
Fig 4. Pin configuration for TFBGA36
SC16C852V_4
Product data sheet
www.DataSheet.in
Rev. 04 — 14 January 2008
© NXP B.V. 2008. All rights reserved.
5 of 54

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SC16C852V arduino
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[2] These registers are accessible only when LCR[7] is a logic 1.
[3] Second special registers are accessible only when EFCR[0] = 1.
[4] Enhanced feature registers are only accessible when LCR = 0xBF.
[5] First extra feature registers are only accessible when EFCR[2:1] = 01b.
[6] Second extra feature registers are only accessible when EFCR[2:1] = 10b.
6.4 FIFO operation
6.4.1 32-byte FIFO mode
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
First Extra Register Set are empty (0x00) the transmit and receive trigger levels are set by
FCR[7:4]. In this mode the transmit and receive trigger levels are backward compatible to
the SC16C652B (see Table 5), and the FIFO sizes are 32 entries. The transmit and
receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]). It should be
noted that the user can set the transmit trigger levels by writing to the FCR, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes a
time-out function to ensure data is delivered to the external CPU (see Section 6.8). Please
refer to Table 12 and Table 13 for the setting of FCR[7:4].
Table 5. Interrupt trigger level and flow control mechanism
(FCR[7:6, 5:4]) INTA/INTB pin activation
RX TX
Negate RTSA/RTSB
or send Xoff
[00, 00]
8
16 8
[01, 01]
16
8
16
[10, 10]
24
24
24
[11, 11]
28
30
28
Assert RTSA/RTSB
or send Xon
0
7
15
23
6.4.2 128-byte FIFO mode
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the First Extra Register
Set contains any value other than 0x00, the transmit and receive trigger levels are set by
TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the transmit
FIFO, and the transmit trigger levels can be set to any value between 1 and 128 with
granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive trigger
levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
6.5 Hardware flow control
When automatic hardware flow control is enabled, the SC16C852V monitors the CTSx pin
for a remote buffer overflow indication and controls the RTSx pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTSx transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16C852V will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTSx input returns to a logic 0, indicating more data
may be sent.
SC16C852V_4
Product data sheet
Rev. 04 — 14 January 2008
© NXP B.V. 2008. All rights reserved.
11 of 54
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