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PDF MAX11211 Data sheet ( Hoja de datos )

Número de pieza MAX11211
Descripción (MAX11209 / MAX11211) Delta-Sigma ADCs
Fabricantes Maxim Integrated Products 
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DataSheet.in
19-5473; Rev 0; 8/10
EVAALVUAAILTAIOBNLEKIT
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
General Description
The MAX11209/MAX11211 are ultra-low-power (< 300FA
active current), high-resolution, serial-output ADCs.
These devices provide the highest resolution per unit
power in the industry, and are optimized for applications
that require very high dynamic range with low power,
such as sensors on a 4mA to 20mA industrial control
loop. Optional input buffers provide isolation of the sig-
nal inputs from the switched capacitor sampling network
allowing these converters to be used with high-imped-
ance sources without compromising available dynamic
range or linearity. The devices provide a high-accuracy
internal oscillator that requires no external components.
When used with the specified data rates, the internal
digital filter provides more than 100dB rejection of 50Hz
or 60Hz line noise. The devices are configurable using
the SPI™ interface and include four GPIOs that can be
used for external mux control. The MAX11209 includes
digital programmable gain of 1 to 128.
The MAX11209/MAX11211 operate over the -40NC to
+85NC temperature range, and are available in a 16-pin
QSOP package.
Applications
Sensor Measurement (Temperature and
Pressure)
Portable Instrumentation
Battery Applications
Weigh Scales
Features
S 18-Bit Noise-Free Resolution
S 570nVRMS Noise at 10sps, ±3.6VFS Input
S 3ppm INL (typ), 15ppm (max)
S No Missing Codes
S Ultra-Low Power Dissipation
Operating-Mode Current Drain < 300µA (max)
Sleep-Mode Current Drain < 0.4µA
S Programmable Gain (1 to 128) (MAX11209)
S Four SPI-Controlled GPIOs for External Mux
Control
S 2.7V to 3.6V Analog Supply Voltage Range
S 1.7V to 3.6V Digital and I/O Supply Voltage Range
S Fully Differential Signal and Reference Inputs
S High-Impedance Inputs
Optional Input Buffers on Both Signal and
Reference Inputs
S > 100dB (min) 50Hz/60Hz Rejection
S SPI-, QSPI™-, MICROWIRE™-Compatible Serial
Interface
S On-Demand Offset and Gain Self-Calibration and
System Calibration
S User-Programmable Offset and Gain Registers
S -40°C to +85°C Operating Temperature Range
S ±2kV ESD Protection
S Lead(Pb)-Free and RoHS-Compliant QSOP
Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX11209EEE+
MAX11211EEE+
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
RESOLUTION
(BITS)
24
20
18
16
4-WIRE SPI, 16-PIN QSOP,
PROGRAMMABLE GAIN
MAX11210
MAX11206
MAX11209
MAX11213
4-WIRE SPI,
16-PIN QSOP
MAX11200
MAX11207
MAX11211
MAX11203
2-WIRE SERIAL,
10-PIN μMAX
MAX11201 (with buffers)
MAX11202 (without buffers)
MAX11208
MAX11212
MAX11205
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX11211 pdf
DataSheet.in
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Typical Operating Characteristics
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = 2.5V; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25NC.)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE
(NO BUFFERS ENABLED)
260
LINEF = 0, LINEF = 1
240
220
TA = +85°C
200
180 TA = +25°C
160
140
120
2.70
TA = -45°C
LINEF = 1
2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE
(SIGNAL OR REFERENCE BUFFERS ENABLED)
260
240
TA = +85°C
220
200 TA = +25°C
180 TA = -45°C
160
SIGNAL BUFFERS
140
120
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE
(SIGNAL AND REFERENCE BUFFERS ENABLED)
280
260
TA = +85°C
240
220 TA = +25°C
200
TA = -45°C
180
160
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
ANALOG SLEEP CURRENT
vs. AVDD VOLTAGE
1.0
TA = -45°C, +25°C, +85°C
0.8
0.6
0.4
TA = -45°C
0.2
TA = +85°C
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD VOLTAGE (V)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (LINEF = 0)
300
250
TOTAL
200
VAVDD = 3.0V
150
100
VDVDD = 1.8V
50
0
-45 -25 -5 15 35 55 75 95
TEMPERATURE (°C)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (LINEF = 1)
300
250
TOTAL
200
VAVDD = 3.0V
150
100
50 VDVDD = 1.8V
0
-45 -25 -5 15 35 55 75 95
TEMPERATURE (°C)
SLEEP CURRENT vs. TEMPERATURE
1.0
0.8
0.6
0.4 TOTAL
DVDD
0.2
AVDD
0
-45 -25 -5 15 35 55 75 95
TEMPERATURE (°C)
DIGITAL ACTIVE CURRENT
vs. DVDD VOLTAGE
130
LINEF = 0, LINEF = 1
120 TA = -45°C, +25°C, +85°C
110
TA = +85°C
100
90 LINEF = 0
80
70 TA = -45°C
60
50 LINEF = 1
40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DVDD VOLTAGE (V)
DIGITAL SLEEP CURRENT
vs. DVDD VOLTAGE
3.0
2.5
2.0
TA = -45°C
1.5 TA = +25°C
1.0 TA = +85°C
0.5
0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
DVDD VOLTAGE (V)
_______________________________________________________________________________________   5

5 Page





MAX11211 arduino
DataSheet.in
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Table 3a. Example of Self-Calibration
REGISTER
BIT
STEP
DESCRIPTION
SCOC
SCGC
SOC
SGC
1 Initial power-up
2 Enable self-calibration registers
3 Self-calibration, DIN = 10010000
0x000000
0x000000
0x00007E
0x000000
0x000000
0xBFD345
0x000000
0x000000
0x000000
0x000000
0x000000
0x000000
Table 3b. Example of System Calibration
REGISTER
STEP
DESCRIPTION
SCOC
SCGC
SOC
SGC
1
1
1
11
10
10
BIT
1
0
0
1 Initial power-up
0x000000 0x000000 0x000000 0x000000 1 1 1 1
2 Enable self-calibration registers
0x000000 0x000000 0x000000 0x000000 1 1 0 0
3 Self-calibration, DIN = 10010000
0x00007E 0xBFD345 0x000000 0x000000 1 1 0 0
4 Enable system offset register
0x00007E 0xBFD345 0x000000 0x000000 1 0 0 0
5 System-calibration offset, DIN = 1010000 0x00007E 0xBFD345 0xFFEE1D 0x000000 1 0 0 0
6 Enable system gain register
0x00007E 0xBFD345 0xFFEE1D 0x000000 0 0 0 0
7 System-calibration gain, DIN = 1011000 0x00007E 0xBFD345 0xFFEE1D 0x81CB5B 0 0 0 0
Noise vs. Data Rate
The devices offer software-selectable internal oscillator
frequencies as well as software-selectable output data
rates. The LINEF bit in the CTRL1 register (Table 12)
determines the internal oscillator frequency. The RATE
bits in the command byte (Table 8) determine the ADC’s
output data rate. The devices also offer the option of
running in zero latency single-cycle conversion mode
(Table 2) or continuous conversion mode (Table 1). Set
SCYCLE = 0 in the CTRL1 register (Table 12) to run in
continuous conversion mode and SCYCLE = 1 for single-
cycle conversion mode.
Single-cycle conversion mode gives an output result with
no data latency. The devices output data up to 100sps
(2.048MHz internal oscillator) or 120sps (2.4576MHz
internal oscillator) with no data latency. In continuous
conversion mode, the output data rate is four times the
single-cycle conversion mode, for sample rates up to
400sps or 480sps. In continuous conversion mode, the
output data requires three additional 24-bit cycles to
settle from an input step.
Digital Filter
The devices include a SINC4 digital filter that produces
spectral nulls at the multiples of the data rate. For all
data rates less than 30sps, a spectral null occurs at the
line frequency of 60Hz and is guaranteed to attenuate
60Hz normal-mode components by more than 100dB.
Simultaneous 50Hz and 60Hz attenuation can be accom-
plished by using an external clock with a frequency of
2.25275MHz. This guarantees a minimum of 80dB rejec-
tion at 50Hz and 85dB rejection at 60Hz. The SINC4 filter
has a -3dB frequency equal to 24% of the data rate. See
Figures 1 and 2.
GPIOs
The devices provide four GPIO ports. When set as out-
puts, these digital I/Os can be used to drive the digital
inputs to a multiplexer or multichannel switch. Figure 3
details an example where four single-ended signals are
multiplexed in a break-before-make switching sequence,
using the MAX313, a quad SPST analog switch.
The devices’ GPIO ports are configurable through the
CTRL2 register. See Table 13. To select AIN1, write the
command to CTRL2 according to Table 4a. This selects
all GPIOs as outputs, as well as setting all logic signals
to 0 except the selected channel AIN1.
To select channel AIN3 next, it is a good idea to set all
switches to a high-impedance state first (see Table 4b).
Then select channel AIN3 by driving IN3 high (see
Table 4c).
______________________________________________________________________________________   11

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