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PDF OPA333 Data sheet ( Hoja de datos )
| Número de pieza | OPA333 | |
| Descripción | microPOWER CMOS OPERATIONAL AMPLIFIERS Zer-PI Drift Series | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de OPA333 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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OPA333
OPA2333www.DataSheet4U.com
SBOS351 − MARCH 2006
1.8V, microPOWER
CMOS OPERATIONAL AMPLIFIERS
Zerj-Drift Series
FEATURES
D LOW OFFSET VOLTAGE: 10µV (max)
D ZERO DRIFT: 0.05µV/°C (max)
D 0.01Hz to 10Hz NOISE: 1.1µVPP
D QUIESCENT CURRENT: 17µA
D SINGLE-SUPPLY OPERATION
D SUPPLY VOLTAGE: 1.8V to 5.5V
D RAIL-TO-RAIL INPUT/OUTPUT
D microSIZE PACKAGES: SC70 and SOT23
APPLICATIONS
D TRANSDUCER APPLICATIONS
D TEMPERATURE MEASUREMENTS
D ELECTRONIC SCALES
D MEDICAL INSTRUMENTATION
D BATTERY-POWERED INSTRUMENTS
D HANDHELD TEST EQUIPMENT
0.1Hz TO 10Hz NOISE
1s/div
DESCRIPTION
The OPA333 series of CMOS operational amplifiers uses
a proprietary auto-calibration technique to simultaneously
provide very low offset voltage (10µV max) and near-zero
drift over time and temperature. These miniature,
high-precision, low quiescent current amplifiers offer
high-impedance inputs that have a common-mode range
100mV beyond the rails and rail-to-rail output that swings
within 50mV of the rails. Single or dual supplies as low as
+1.8V (±0.9V) and up to +5.5V (±2.75V) may be used.
They are optimized for low-voltage, single-supply
operation.
The OPA333 family offers excellent CMRR without the
crossover associated with traditional complementary input
stages. This design results in superior performance for
driving analog-to-digital converters (ADCs) without
degradation of differential linearity.
The OPA333 (single version) is available in the SC70-5,
SOT23-5, and SO-8 packages. The OPA2333 (dual
version) is offered in DFN-8 (3mm x 3mm, available
Q2 ’06) and SO-8 packages. All versions are specified for
operation from −40°C to +125°C.
OUT 1
V− 2
+IN 3
OPA333
5 V+
4 −IN
SOT23−5
+IN 1
V− 2
−IN 3
OPA333
5 V+
4 OUT
SC70−5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2006, Texas Instruments Incorporated
www.ti.com
1 page  
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = +5V, and CL = 0pF, unless otherwise noted.
INPUT BIAS CURRENT vs COMMON−MODE VOLTAGE
100
80
60 −IB
40
VS = 5V
20
0
−20
−40
−60
+IB
−80
−100
012345
Common−Mode Voltage (V)
QUIESCENT CURRENT vs TEMPERATURE
25
20
VS = 5.5V
15
VS = 1.8V
10
5
0
−50
−25
0 25 50 75
Temperature (_C)
100 125
SMALL−SIGNAL STEP RESPONSE
G = +1
RL = 10kΩ
Time (5µs/div)
OPA333
OPA2333
www.DataSheet4U.com
SBOS351 − MARCH 2006
INPUT BIAS CURRENT vs TEMPERATURE
200
150 −IB
VS = 5.5V
VS = 1.8V
100
−IB
50
0
+IB
−50
−100
−150
+IB
−200
−50
−25
0 25 50 75
Temperature (_ C)
100 125
LARGE−SIGNAL STEP RESPONSE
G=1
RL = 10kΩ
Time (50µs/div)
POSITIVE OVER−VOLTAGE RECOVERY
0
Input
Output
1 0k Ω
+2 .5V
1kΩ
0
OPA333
−2.5V
Time (50µs/div)
5
5 Page 
www.ti.com
DFN PACKAGE
The OPA2333 is offered in an DFN-8 package (also known
as SON). The DFN is a QFN package with lead contacts
on only two sides of the bottom of the package. This
leadless package maximizes board space and enhances
thermal and electrical characteristics through an exposed
pad.
DFN packages are physically small, have a smaller routing
area, improved thermal performance, and improved
electrical parasitics. Additionally, the absence of external
leads eliminates bent-lead issues.
The DFN package can be easily mounted using standard
printed circuit board (PCB) assembly techniques. See
Application Note QFN/SON PCB Attachment (SLUA271)
and Application Report Quad Flatpack No-Lead Logic
Packages (SCBA017), both available for download at
www.ti.com.
The exposed leadframe die pad on the bottom of the
package should be connected to V− or left
unconnected.
OPA333
OPA2333
www.DataSheet4U.com
SBOS351 − MARCH 2006
DFN LAYOUT GUIDELINES
The exposed leadframe die pad on the DFN package
should be soldered to a thermal pad on the PCB. A
mechanical drawing showing an example layout is
attached at the end of this data sheet. Refinements to this
layout may be necessary based on assembly process
requirements. Mechanical drawings located at the end of
this data sheet list the physical dimensions for the package
and pad. The five holes in the landing pattern are optional,
and are intended for use with thermal vias that connect the
leadframe die pad to the heatsink area on the PCB.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests. Even
with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet OPA333.PDF ] | |
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