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PDF EZASC Data sheet ( Hoja de datos )

Número de pieza EZASC
Descripción Chip 3-Terminal Capacitor Array
Fabricantes Panasonic Semiconductor 
Logotipo Panasonic Semiconductor Logotipo



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No Preview Available ! EZASC Hoja de datos, Descripción, Manual

Chip 3-Terminal Capacitor Array
Type: EZASC
EZANC
GND
GND
Chip 3-Terminal Cwawpwa.DcatiatSohreetA4Ur.croamy
Features
1. Suitable for EMI suppression filtering
The low residual inductance at high frequency range provides effective reduction of noise
Equivalent noise reduction to the EMI filters with low cost design
2. Compact design for high density PWB assembly
EZASC : 4.0 mm ҂ 2.1 mm ҂ 0.65 mm, 0.8 mm pitch
EZANC : 6.4 mm ҂ 3.1 mm ҂ 0.75 mm, 1.27 mm pitch
Flat and square packages suitable for high speed automatic placement machine
3. Superior mountability with concave terminals
Firm solder joint (2 times that of convex terminal type)
Self-aligning placement during reflow soldering
<Effect of high density placing, PWB space saving>
(4 line mounting)
I/O I/O
3-Terminal Capacitors or EMI Filters
I/O I/O
EZASC: 0.8 mm pitch
EZANC: 1.27 mm pitch
Digital cordless phone
RF Circuit
(EZA SC)
Digital Control Circuit
Prevent high frequency harmonic
noise to RF circuits
Recommended Applications
Digital equipment such as PCs, printers, HDD, PCMCIA cards, PDAs, and word processors
Communication equipment, digital cordless phones, automobile phones, GSM, PHS, DECT
Digital audio and video equipment
Electronic musical instruments, and other digital devices
Design and specifications are each subject to change without notice. Ask factory for the current technical specifications before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Feb. 2006

1 page




EZASC pdf
Recommended Soldering Conditions
Recommendations and precautions are described below.
Recommended soldering conditions for reflow
·Reflow soldering shall be performed a maximum of
two times.
·Please contact us for additional information when
used in conditions other than those specified.
·Please measure the temperature of the terminals and
study every kind of solder and printed circuit board
for solderability before actual use.
Peak
Preheating
Heating
Chip 3-Terminal Cwawpwa.DcatiatSohreetA4Ur.croamy
For soldering (Example : Sn/Pb)
Preheating
Main heating
Peak
Temperature
140 °C to 160 °C
Above 200 °C
235 ± 5 °C
Time
60 s to 120 s
30 s to 40 s
max. 10 s
For lead-free soldering (Example : Sn/Ag/Cu)
Temperature
Time
Preheating
150 °C to 180 °C 60 s to 120 s
Main heating Above 230 °C 30 s to 40 s
Peak
max. 260 °C
max. 10 s
Time
Flow Soldering
We do not recommend flow soldering to the Chip 3-Terminal Capacitor Array: EZASC, because solder
bridging may occur due to the narrow 0.8 mm pitch of EZASC. Please contact us regarding flow soldering
of EZANC type.
Safety Precautions
The following are precautions for individual products. Please also refer to the precautions common to EMI Filters,
Fuses, and Sensors(MR Elements) shown on page EX2 of this catalog.
1. Take measures against mechanical stress during and after mounting of Chip 3-Terminal Capacitor Array (hereafter
called the capacitor arrays) so as not to damage their electrodes and protective coatings.
Be careful not to misplace the capacitor arrays on the land patterns. Otherwise, solder bridging may occur.
2. Do not use halogen-based or other high-activity flux. Otherwise, the residue may impair the capacitors arrays'
performance and/or reliability.
3. When soldering with a soldering iron, never touch the capacitor arrays' bodies with the tip of the soldering iron. When
using a soldering iron with a high temperature tip, finish soldering as quickly as possible (within three seconds at 350 °
C max.).
4. As the amount of applied solder becomes larger, the mechanical stress applied to the capacitor arrays increases,
causing problems such as cracks and faulty characteristics. Avoid applying an excessive amounts of solder.
5. Do not apply shock to the capacitor arrays or pinch them with a hard tool (e.g. pliers and tweezers). Otherwise, the
capacitor arrays' protective coatings and bodies may be chipped, affecting their performance.
6. Avoid excessive bending of printed circuit boards in order to protect the capacitor arrays from abnormal stress.
7. The static capacitance may decrease by a few percent from the time of shipment due to the characteristics peculiar to
dielectric materials having a high dielectric constant.
Design and specifications are each subject to change without notice. Ask factory for the current technical specifications before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Feb. 2006

5 Page










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