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PDF MR4010 Data sheet ( Hoja de datos )

Número de pieza MR4010
Descripción Superscalar Microprocessor
Fabricantes LSI Logic 
Logotipo LSI Logic Logotipo



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MiniRISC™ MR4010
Superscalar
Microprocessor
Reference Device
www.DataSheet4U.com
Contents
1 MR4010 Features
2 MR4010 Functional Blocks
2.1 CW4010 Shell
2.2 Synchronous DRAM Controller (DRAMC)
2.3 SCbus to Local I/O Bus (Lbus) Controller (SCLC)
2.4 PLL Clock Circuit
3 MR4010 Programming Model
4 Signal Descriptions
4.1 SCbus Interface
4.2 External Buffering for SCbus Signals
4.3 CW4010 Shell Interface
4.4 Mbus Interface
4.5 Lbus Interface
4.6 Phase-Locked Loop (PLL) Clock Signals
4.6 Test Signals
4.7 CW4010 Core Monitor Signals
5 PLL Circuit
6 System Configuration
6.1 CW4010 CCC Register
6.2 Lbus Controller Registers
7 MR4010 Memory Map
8 CW4010 Instruction Set Summary
9 DRAM Controller and Memory Bus
9.1 DRAM Types and Available DRAM Address Area
9.2 Memory Interface
9.3 Address Bit Assignment
9.4 DRAM Modes and Programmable Configurations
9.5 DRAM Refresh
9.6 DRAM Commands
9.7 Initializing the DRAM and Programming the Mode
November 1996
Copyright © 1996 by LSI Logic Corporation. All rights reserved.
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MiniRISC MR4010 Superscalar Microprocessor
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MR4010 arduino
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The CW4010 core executes all MIPS-II 32-bit based instructions except
for multiply/divide instructions, which are handled by the Multiply/Divide
unit. The microprocessor is implemented as efficient dual six-stage
pipelines. The pipelines have the traditional instruction fetch and execu-
tion stages. An additional queuing (Q) stage (one of the instruction fetch
stages) removes the penalty cycle when a branch instruction is executed.
Standard MIPS compiled code for R3000 and R4000 processors runs on
the CW4010 core.
The CW4010 has an extended instruction set and implements ADDCIU
(Add with Circular Mask Immediate Unsigned), MADD/MADDU (Multiply
Accumulate (Unsigned)), MSUB/MSUBU (Multiply Subtract (Unsigned)),
FFS/FFC (Find First Set/Clear Bit), SELSR/SELSL (Select and Shift
Right/Left), WAITI (Wait Interrupt) and FLUSHID (Flush Instruction/Data
Cache) instructions.
2.1.2 Multiply/Divide
The multiply/divide module supports Multiply-Add/Subtract operations as
well as Multiply and Divide. The Multiply instruction executes in three
cycles. The Multiply-Add/Subtract instruction is optimized to two cycles.
2.1.3 Memory Management Unit (MMU)
The MMU has 32 single-page entries, which are a subset of the R4000
32-bit addressing mode. Each page is individually specified to be 4 Kbyte
or 16 Mbyte and may be cached or uncached.
2.1.4 Writeback Buffer
The CW4010 uses this buffer when the Dcache operates in Writeback
mode. When a cache miss occurs at a dirty line, the dirty data is written
into the Writeback Buffer instead of the main memory. This reduces the
latency of the cache refill for missed addresses. Data in the Writeback
Buffer is written into the main memory after the refill is completed.
2.1.5 Caches
The MR4010 has separate instruction and data caches—Icache and
Dcache—that are part of the CW4010 shell. Both caches can be orga-
nized as direct-mapped or two-way set-associative caches. The cache
controllers support configurations of 1, 2, 4, or 8 Kbytes for each set.
MiniRISC MR4010 Superscalar Microprocessor
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