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PDF EN25Q32A Data sheet ( Hoja de datos )

Número de pieza EN25Q32A
Descripción 32 Megabit Serial Flash Memory
Fabricantes Eon Silicon Solution 
Logotipo Eon Silicon Solution Logotipo



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EN25Q32A
EN25Q32A
32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
Single power supply operation
- Full voltage range: 2.7-3.6 volt
Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
32 M-bit Serial Flash
- 32 M-bit/4096 K-byte/16384 pages
- 256 bytes per programmable page
Standard, Dual or Quad SPI
- Standard SPI: CLK, CS#, DI, DO, WP#
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
High performance
- 100MHz clock rate for one data bit
- 80MHz clock rate for two data bits
- 80MHz clock rate for four data bits
Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
Uniform Sector Architecture:
- 1024 sectors of 4-Kbyte
- 64 blocks of 64-Kbyte
- Any sector or block can be erased individually
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
High performance program/erase speed
- Page program time: 1.3ms typical
- Sector erase time: 90ms typical
- Block erase time 500ms typical
- Chip erase time: 25 seconds typical
Lockable 512 byte OTP security sector
Minimum 100K endurance cycle
Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN
- 8 pins PDIP
- All Pb-free packages are RoHS compliant
Industrial temperature Range
GENERAL DESCRIPTION
The EN25Q32A is a 32 Megabit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q32A supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI),
DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 80MHz are supported allowing
equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the
Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The EN25Q32A is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25Q32A can be configured to protect part of the memory as the software protected mode. The
device can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com

1 page




EN25Q32A pdf
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EN25Q32A
MEMORY ORGANIZATION
The memory is organized as:
z 4,194,304 bytes
z Uniform Sector Architecture
64 blocks of 64-Kbyte
1024 sectors of 4-Kbyte
z 16384 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com

5 Page





EN25Q32A arduino
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EN25Q32A
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Status Register. The Status Register contains a number of status and control bits that can be read or
set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
WPDIS bit. The Write Protect disable (WPDIS) bit, non-volatile bit, when it is reset to “0” (factory
default) to enable WP# function or is set to “1” to disable WP# function (It can be floating during SPI
mode.)
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25Q32A provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. C, Issue Date: 2009/10/13
www.eonssi.com

11 Page







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