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PDF L5954 Data sheet ( Hoja de datos )
| Número de pieza | L5954 | |
| Descripción | Multiple multifunction voltage regulator | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L5954
Multiple multifunction voltage regulator for car radio
Features
■ 5 regulators:
– 10 V (350 mA)
– 8.5 V (175 mA)
– 5 V (350 mA)
– 5 V (250 mA)
– 8 V/10 V (1 A)
■ All regulators are low dropout
■ 3 high side drivers:
– 2 A (HSD1)
– 0.45 A (HSD2 and HSD3)
■ No external charge pump capacitors are
required
■ Standby mode controlled by 3 input pins:
– Enable for Reg2 and Reg3
– I2C bus for Reg1, Reg4, Reg5, Hsd1, Hsd2,
Hsd3
■ Individual thermal shutdown
■ Independent current limiting
■ Short circuit protection
■ Load dump protection and overvoltage
shutdown
■ ESD protected
Multiwatt15
Description
The L5954 is an integration of three high side
drivers and five regulators developed to provide
the power for an audio system.
The outputs of the IC are controlled via the I2C
bus and the Enable input.
External protection must be provided for reverse
battery protection.
Table 1.
Device summary
Order code
L5954
Package
Multiwatt15
Packing
Tube
July 2010
Doc 17717 Rev 1
1/15
www.st.com
1
1 page  
L5954
1
www.DataSheet4U.com
Block and pins connection diagrams
Block and pins connection diagrams
Figure 1. Block diagram
BAT
GND
VOLTAGE
REFERENCE
VREF
ENABLE
SCL
SDA
8.5 & 5V
ENABLE
PC OUTPUT
CONTROL
CURRENT
LIMIT
PROTECTION
LOGIC
INDIVIDUAL
THERMAL
SHUTDOWN
OVERVOLTAGE
PROTECTION
Figure 2. Pins connection (top view)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Doc 17717 Rev 1
REG 1
10V 350mA
REG 2
8.5V 175mA
REG 3
5V 350mA
REG 4
8V/10V 1A
REG 5
5V 250mA
REG1
REG2
REG3
REG4
REG5
DRIVE 1
2A
HSD1
DRIVE 2
450mA
HSD2
DRIVE 3
450mA
HSD3
D99AU1002
REG4
BAT
REG5
REG3
REG2
REG1
VREF
GND
SCL
Enable
SDA
HSD3
HSD2
BAT
HSD1
D99AU1006
5/15
5 Page 
L5954
www.DataSheet4U.com
Functional description
3.1.4 Overvoltage
The IC will not operate if the BAT voltage reaches 27 V typ. or above.
Figure 3. Definition of timing on the I2C bus.
SDA
tBUP
SCL
P
S
tLOW
tR
tHD;DAT
tHD;DAT
tHIGH
tF
tHD;STA
tSP
tSU;DAT
tSU;STA
Sr
D99AU1007
tSU;STO
P
Figure 4. Typical application circuit.
EN ENABLE
REG1
FBATT BAT REG2
0.1μF
1000μF
VREF
VREF
REG3
REG4
REG4
SCL
SDA
GND
REG5 REG5
C14
10μF
C12
10μF
HSD1
HSD2
HSD3
HSD1
HSD2
HSD3
D99AU1010A
(*) ESR of output capacitors should be between 0.1Ω and 5.0Ω.
REG3
C10
10μF
REG2
C8
10μF
REG1
C6
10μF
3.1.5 Write mode
CHIP ADDRESS
S
MSB
LSB
0A
DATA BYTE
MSB
A .. ..
LSB
P
S = START condition - SDA goes from high to low while SCL is high
A = Acknowledge - the device being written to, pulls down on data line (SDA) during the
acknowledge clock pulse.
P = STOP condition - SDA goes from low to high while SCL is high.
Doc 17717 Rev 1
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet L5954.PDF ] | |
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