DataSheet.es    


PDF 71M6531D Data sheet ( Hoja de datos )

Número de pieza 71M6531D
Descripción Energy Meter IC
Fabricantes TERIDIAN Semiconductor 
Logotipo TERIDIAN Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de 71M6531D (archivo pdf) en la parte inferior de esta página.


Total 70 Páginas

No Preview Available ! 71M6531D Hoja de datos, Descripción, Manual

Simplifying System IntegrationTM
www.DataSheet4U.com
71M6531D/F, 71M6532D/F
Energy Meter IC
DATA SHEET
GENERAL DESCRIPTION
The Teridian 71M6531D/F and 71M6532D/F are highly
integrated SOCs with an MPU core, RTC, FLASH and LCD
driver. Teridian’s patented Single Converter Technology®
with a 22-bit delta-sigma ADC, four analog inputs, digital
temperature compensation, precision voltage reference, battery
voltage monitor and 32-bit computation engine (CE) supports
a wide range of residential metering applications with very few
low-cost external components.
A 32-kHz crystal time base for the entire system and internal
battery backup support for RAM and RTC further reduce system
cost. The IC supports 2-wire, and 3-wire single-phase and
dual-phase residential metering along with tamper-detection
mechanisms. The 71M6531D/F offers single-ended inputs for
two current channels and two single-ended voltage inputs.
The 71M6532D/F has two differential current inputs and three
single-ended voltage inputs.
Maximum design flexibility is provided by multiple UARTs, I2C,
μWire, up to 21 DIO pins and in-system programmable FLASH
memory, which can be updated with data or application code
in operation.
A complete array of ICE and development tools, programming
libraries and reference designs enable rapid development and
certification of TOU, AMR and Prepay meters that comply with
worldwide electricity metering standards.
CT/SHUNT
A
NEUTRAL
CT
B
LOAD
LOAD
POWER SUPPLY
AMR
RX/DIO1
IR TX/DIO2
POWER
FAULT
32 kHz
ADC
IAP*
IAN*
VA
IBP*
IBN*
VB
V3.3A
V3.3
SYS
GNDA GNDD
PWR MODE
TERIDIAN CONTROL
71M6531 WAKE-UP
71M6532 REGULATOR
VBAT
V2.5
VOLTAGE REF
VREF
VBIAS
TEMP
SENSOR
RAM
LCD & DIO
COM0..3
LCD SEG
SERIAL PORTS
TX
RX
SENSE
DRIVE/MOD
COMPARATOR
V1
OSC/PLL
XIN
XOUT
FLASH
MEMORY
COMPUTE
ENGINE
MPU
TIMERS
RTC
ICE I/F
SEG/DIO
SPI
ICE_E
* Differential pins only on 6532D/F
02/18/2009
BATTERY
88. 88. 8888
I2C or µWire
EEPROM
TEST PULSES
SPI HOST
V3P3D
GNDD
June 2010
FEATURES
Wh accuracy < 0.1% over 2000:1 current
range
Exceeds IEC62053/ANSI C12.20 standards
Four sensor inputs
Low-jitter Wh and VARh plus two additional
pulse test outputs (4 total, 10 kHz maximum)
with pulse count
Four-quadrant metering
Tamper detection (Neutral current with CT,
Rogowski or shunt, magnetic tamper input)
Line frequency count for RTC
Digital temperature compensation
Sag detection for phase A and B
Independent 32-bit compute engine
46-64 Hz line frequency range with same
calibration. Phase compensation (± 7°)
Three battery modes with wake-up on timer
or push-button:
Brownout mode (52 µA typ.)
LCD mode (21 µA typ., DAC active)
Sleep mode (0.7 µA typ.)
Energy display during mains power failure
39 mW typical consumption @ 3.3 V, MPU
clock frequency 614 kHz
22-bit delta-sigma ADC with 3360 Hz or
2520 Hz sample rate
8-bit MPU (80515),1 clock cycle per instruction,
10 MHz maximum, with integrated ICE for
debug
RTC for TOU functions with clock-rate adjust
register
Hardware watchdog timer, power fail monitor
LCD driver with 4 common segment drivers:
Up to 156 (71M6531D/F) or 268 pixels
(71M6532D/F)
Up to 22 (71M6531D/F) or 43 (71M6532D/F)
general-purpose I/O pins. Digital I/O pins
compatible with 5 V inputs
32 kHz time base
High-speed slave SPI interface to data RAM
Two UARTs for IR and AMR, IR driver with
modulation
FLASH memory with security and in-system
program update:
128 KB (71M6531D/32D)
256 KB (71M6531F/32F)
4 KB MPU XRAM
Industrial temperature range
68-pin QFN package for 71M6531D/F pin-
compatible with 71M6521, 100-pin LQFP
package for 71M6532D/F, lead free
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation 1

1 page




71M6531D pdf
FDS 6531/6532 005
Data Sheet 71M6531D/F-w7w1wM.D6a5ta3S2heDet/4FU.com
Figures
Figure 1: 71M6531D/F IC Functional Block Diagram ................................................................................... 8
Figure 2: 71M6532D/F IC Functional Block Diagram ................................................................................... 9
Figure 3: General Topology of a Chopped Amplifier .................................................................................. 13
Figure 4: CROSS Signal with CHOP_E[1:0] = 00 ....................................................................................... 13
Figure 5: AFE Block Diagram (Shown for the 71M6532D/F)...................................................................... 14
Figure 6: Samples from Multiplexer Cycle .................................................................................................. 18
Figure 7: Accumulation Interval .................................................................................................................. 18
Figure 8: Interrupt Structure ........................................................................................................................ 35
Figure 9: Optical Interface........................................................................................................................... 41
Figure 10: Connecting an External Load to DIO Pins................................................................................. 45
Figure 11: 3-Wire Interface. Write Command, HiZ=0 ................................................................................ 48
Figure 12: 3-Wire Interface. Write Command, HiZ=1 ................................................................................ 48
Figure 13: 3-Wire Interface. Read Command. ........................................................................................... 49
Figure 14: 3-Wire Interface. Write Command when CNT=0...................................................................... 49
Figure 15: 3-Wire Interface. Write Command when HiZ=1 and WFR=1 ................................................... 49
Figure 16: SPI Slave Port: Typical Read and Write operations .................................................................. 51
Figure 17: Functions defined by V1 ............................................................................................................ 52
Figure 18: Voltage, Current, Momentary and Accumulated Energy ........................................................... 54
Figure 19: Timing Relationship between ADC MUX, Compute Engine ...................................................... 55
Figure 20: RTM Output Format ................................................................................................................... 55
Figure 21: Operation Modes State Diagram ............................................................................................... 56
Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns ...................... 59
Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together........................................................ 59
Figure 24: Power-Up Timing with VBAT only.............................................................................................. 60
Figure 25: Wake Up Timing ........................................................................................................................ 61
Figure 26: MPU/CE Data Flow.................................................................................................................... 62
Figure 27: MPU/CE Communication........................................................................................................... 62
Figure 28: Resistive Voltage Divider........................................................................................................... 63
Figure 29: CT with Single Ended (Left) and Differential Input (Right) Connection ..................................... 63
Figure 30: Resistive Shunt (Left) and Rogowski Sensor (Right) Connection ............................................. 63
Figure 31: Connecting LCDs....................................................................................................................... 66
Figure 32: I2C EEPROM Connection .......................................................................................................... 66
Figure 33: Three-Wire EEPROM Connection ............................................................................................. 67
Figure 34: Connections for UART0............................................................................................................. 67
Figure 35: Connection for Optical Components.......................................................................................... 68
Figure 36: Voltage Divider for V1................................................................................................................ 68
Figure 37: External Components for the RESET Pin: Push-button (Left), Production Circuit (Right) ........ 69
Figure 38: External Components for the Emulator Interface ...................................................................... 69
Figure 39: Connecting a Battery ................................................................................................................. 70
Figure 40: CE Data Flow: Multiplexer and ADC.......................................................................................... 96
Figure 41: CE Data Flow: Scaling, Gain Control, Intermediate Variables .................................................. 96
Figure 42: CE Data Flow: Squaring and Summation Stages...................................................................... 97
Figure 43: SPI Slave Port (MISSION Mode) Timing ................................................................................. 106
Figure 44: Wh Accuracy, 0.1 A to 200 A at 240 V/50 Hz and Room Temperature .................................. 107
Figure 45: QFN-68 Package Outline, Top and Side View ........................................................................ 108
Figure 46: QFN-68 Package Outline, Bottom View .................................................................................. 108
Figure 47: Pinout for QFN-68 Package..................................................................................................... 109
Figure 48: PCB Land Pattern for QFN 68 Package.................................................................................. 110
Figure 49: PCB Land Pattern for LQFP-100 Package.............................................................................. 111
Figure 50: LQFP-100 Package, Mechanical Drawing............................................................................... 112
Figure 51: I/O Equivalent Circuits ............................................................................................................. 115
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation
5

5 Page





71M6531D arduino
FDS 6531/6532 005
Data Sheet 71M6531D/F-w7w1wM.D6a5ta3S2heDet/4FU.com
1.2.2 Input Multiplexer
The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB
(IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability to
select temperature and the battery voltage. The multiplexer can be operated in two modes:
During a normal multiplexer cycle, the signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins
are selected.
During the alternate multiplexer cycle, the temperature signal (TEMP) and the battery monitor are
selected, along with some of the voltage and/or current signal sources shown in Table 1. To prevent
unnecessary drainage on the battery, the battery monitor is only active when enabled with the BME
bit (0x2020[6]) in the I/O RAM.
The alternate multiplexer cycles are usually performed infrequently (every second or so) by the MPU. In
order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in
the ALT selections. Table 1 details the regular and alternative multiplexer sequences. The computation
engine (CE) fills in missing samples due to an ALT multiplexer sequence.
Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles
Time
Slot
0
1
2
3
Regular Slot
Register
SLOT0_SEL[3:0]
SLOT1_SEL[3:0]
SLOT2_SEL[3:0]
SLOT3_SEL[3:0]
SLOT4_SEL[3:0]
SLOT5_SEL[3:0]
SLOT6_SEL[3:0]
SLOT7_SEL[3:0]
SLOT8_SEL[3:0]
SLOT9_SEL[3:0]
Typical Selections
RAM
Address
0
1
2
3
Signal for
ADC
IA
VB
IB
VA
Alternate Slot
Register
SLOT0_ALTSEL[3:0]
SLOT1_ALTSEL[3:0]
SLOT2_ALTSEL[3:0]
SLOT3_ALTSEL[3:0]
SLOT4_ALTSEL[3:0]
SLOT5_ALTSEL[3:0]
SLOT6_ALTSEL[3:0]
SLOT7_ALTSEL[3:0]
SLOT8_ALTSEL[3:0]
SLOT9_ALTSEL[3:0]
Typical Selections
RAM
Address
A
1
B
3
Signal for
ADC
TEMP
VB
VBAT
VA
The sequence of sampled channels is fully programmable using I/O RAM registers. SLOTn_SEL[3:0]
selects the input for the nth state in a standard multiplexer frame, while SLOTn_ALTSEL[3:0] selects the
input for the nth state in an alternate multiplexer frame. The states shown in Table 1 are examples for
possible multiplexer state sequences.
In a typical application, IA (IAN/IAP) and IB (IBN/IBP) are connected to current transformers that sense
the current on each phase of the line voltage. VA and VB are typically connected to voltage sensors
through resistor dividers.
The multiplexer control circuit (MUX_CTRL signal) controls multiplexer advance, FIR initiation and VREF
chopping. Additionally, MUX_CTRL launches each pass through the CE program. Conceptually,
MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of MUX_CTRL is
governed by MUX_ALT, EQU[2:0], CHOP_E[1:0] and MUX_DIV[3:0].
The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle
and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT
will cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplexer
frame.
Another control input to the MUX is MUX_DIV[3:0]. These four bits can request from 1 to 10 multiplexer
states per frame. The multiplexer always starts at the beginning of its list and proceeds until the number
of states defined by MUX_DIV[3:0] have been converted.
v1.3 © 2005-2010 TERIDIAN Semiconductor Corporation
11

11 Page







PáginasTotal 70 Páginas
PDF Descargar[ Datasheet 71M6531D.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
71M6531DEnergy Meter ICTERIDIAN Semiconductor
TERIDIAN Semiconductor
71M6531FEnergy Meter ICTERIDIAN Semiconductor
TERIDIAN Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar