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PDF 73S1215F Data sheet ( Hoja de datos )
| Número de pieza | 73S1215F | |
| Descripción | 80515 System-on-Chip | |
| Fabricantes | Teridian Semiconductor | |
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Simplifying System Integration™
GENERAL DESCRIPTION
The 73S1215F is a versatile and economical
CMOS System-on-Chip device intended for smart
card reader applications. The circuit features an
ISO 7816 / EMV interface, an USB 2.0 interface
(full-speed 12Mbps device) and a 5x6 PINpad
interface. Maximum design flexibility is supported
with additional features such as 9 user I/Os,
multiple interrupt options, up to 4 programmable
current outputs (to drive external LEDs), and 1
analog voltage input (suitable for DC voltage
monitoring such as battery level detection). Other
built-in hardware interfaces include an
asynchronous serial UART and an I2C interface.
The System-on-Chip is built around an 80515 high
performance core. Its feature and instruction set is
compatible with the industry standard 8051, while
offering one clock-cycle per instruction processing
power (most instructions)With a CPU clock running
up to 24MHz, it results in up to 20 MIPS available
that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA
(for PIN encryption for instance). The circuit
requires a single crystal, which frequency can be
between 6MHz and 12MHz. In addition, a 32768
Hz sub-system oscillator (optional) with an
independent real-time-clock counter enables stand-
alone applications to access an RTC value. The
respective 73S1215F embedded memories are;
64KB Flash program memory, 2KB user XRAM
memory, and 256B IRAM memory. In addition to
these memories are independent FIFOs dedicated
to the ISO7816 UART and to the USB interface.
Overall, the 73S1215F offers a cost effective
solution to implement hand-held PINpad smart card
readers - USB connected, serial connected,
standalone or combo – as well as turnkey smart
card reader modules, USB or ExpressCard® type.
Embedded Flash memory is in-system
programmable and lockable by means of on-silicon
fuses. This makes the Teridian 73S1215F suitable
for both development and production phases.
www.DataSheet4U.com
73S1215F
80515 System-on-Chip with USB,
ISO 7816 / EMV, PINpad and More
DATA SHEET
December 2008
Teridian Semiconductor Corporation offers with
its 73S1215F a very comprehensive set of
software libraries, including the smart card and
USB protocol layers that are pre-approved
against USB, Microsoft WHQL and EMV, as
well as a CCID reference design. Refer to the
73S12xxF Software User’s Guide for a
complete description of the Application
Programming Interface (API Libraries) and
related software modules.
A complete array of development and
programming tools, libraries and demonstration
boards enable rapid development and
certification of smart card readers that meet
most demanding smart card standards.
APPLICATIONS
• Hand-held PINpad smart card readers:
o Connected through USB, serial or
un-connected
o CCID-compliant
• E-banking (MasterCard CAP, etc)
• Smart card reader modules for PC laptops
and desktops: ExpressCard® , USB
• Digital Identification (Secure Login, Gov’t ID, ...)
• General purpose smart card readers
ADVANTAGES
• The ideal balance of cost and features for
high volume, USB-connected PINpad type
of applications:
o Larger built-in Flash / RAM than its
competitors
o Higher performance CPU core
o Powerful In-Circuit- Emulation and
Programming
o A complete set of ready-to-use EMV4.1 /
USB / CCID libraries
Rev. 1.4
© 2008 Teridian Semiconductor Corporation
1
1 page  
DS_1215F_003
73S1215wFwDwa.DtaataSShheeete4Ut .com
Tables
Table 1: 73S1215F Pinout Description ......................................................................................................... 8
Table 2: MPU Data Memory Map................................................................................................................ 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations................................................................................. 18
Table 7: IRAM Special Function Registers Reset Values........................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register Flags...................................................................................................................... 22
Table 10: PSW Bit Functions ...................................................................................................................... 22
Table 11: Port Registers ............................................................................................................................. 23
Table 12: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 25
Table 13: The MCLKCtl Register ................................................................................................................ 25
Table 15: The MPUCKCtl Register ............................................................................................................. 26
Table 17: The INT5Ctl Register .................................................................................................................. 29
Table 19: The MISCtl0 Register.................................................................................................................. 29
Table 21: The MISCtl1 Register.................................................................................................................. 30
Table 23: The MCLKCtl Register ................................................................................................................ 31
Table 25: The PCON Register .................................................................................................................... 32
Table 27: The IEN0 Register....................................................................................................................... 34
Table 29: The IEN1 Register....................................................................................................................... 35
Table 31: The IEN2 Register....................................................................................................................... 35
Table 33: The TCON Register .................................................................................................................... 36
Table 35: The T2CON Register .................................................................................................................. 36
Table 37: The IRCON Register ................................................................................................................... 37
Table 39: External MPU Interrupts.............................................................................................................. 37
Table 40: Control Bits for External Interrupts.............................................................................................. 38
Table 41: Priority Level Groups................................................................................................................... 38
Table 42: The IP0 Register ......................................................................................................................... 38
Table 43: The IP1 Register ......................................................................................................................... 39
Table 44: Priority Levels.............................................................................................................................. 39
Table 45: Interrupt Polling Sequence.......................................................................................................... 39
Table 46: Interrupt Vectors.......................................................................................................................... 39
Table 47: UART Modes............................................................................................................................... 40
Table 48: Baud Rate Generation ................................................................................................................ 40
Table 49: The PCON Register .................................................................................................................... 41
Table 51: The BRCON Register ................................................................................................................. 41
Table 53: The MISCtl0 Register.................................................................................................................. 42
Table 55: The S0CON Register .................................................................................................................. 43
Table 57: The S1CON Register .................................................................................................................. 44
Table 59: The TMOD Register .................................................................................................................... 45
Table 61: Timers/Counters Mode Description ............................................................................................ 46
Table 62: The TCON Register .................................................................................................................... 47
Table 64: The IEN0 Register....................................................................................................................... 48
Table 66: The IEN1 Register....................................................................................................................... 48
Table 68: The IP0 Register ......................................................................................................................... 49
Table 70: The WDTREL Register ............................................................................................................... 49
Table 72: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 50
Table 73: UDIR Control Bit.......................................................................................................................... 50
Table 74: Selectable Controls Using the UxIS Bits..................................................................................... 50
Table 75: The USRIntCtl1 Register ............................................................................................................ 51
Table 76: The USRIntCtl2 Register ............................................................................................................ 51
Table 77: The USRIntCtl3 Register ............................................................................................................ 51
Table 78: The USRIntCtl4 Register ............................................................................................................ 51
Table 79: The RTCCtl Register................................................................................................................... 53
Table 81: The 32-bit RTC Counter.............................................................................................................. 54
Table 82: The 24-bit RTC Accumulator ...................................................................................................... 54
Rev. 1.4
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DS_1215F_003
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1.2 Hardware Overview
The Teridian 73S1215F single smart card controller integrates all primary functional blocks required to
implement a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which
executes up to one instruction per clock cycle (80515), a fully integrated IS0-7816 compliant smart card
interface, expansion smart card interface, full speed USB 2.0 compatible interface, serial interface, I2C
interface, 6 x 5 keypad interface, 4 LED drivers, RAM, FLASH memory, a real time clock (RTC), and a
variety of I/O pins. Figure 1 shows a functional block diagram of the 73S1215F.
1.3 80515 MPU Core
1.3.1 80515 Overview
The 73S1215F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution
of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most
of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(cryptographic calculations, key management, memory management, and I/O management) using the
XRAM special function register MPUCKCtl.
Typical smart card, USB, serial, keyboard, I2C, and RTC management functions are available for the
MPU as part of the Teridian standard library. A standard ANSI “C” 80515-application programming
interface library is available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.
1.3.2 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three
memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory
(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2.
Table 2: MPU Data Memory Map
Address
(hex)
0000-FFFF
0000-07FF
FC00-FFFF
Memory
Technology
Flash Memory
Static RAM
External SFR
Memory Type Typical Usage
Non-volatile
Volatile
Volatile
Program and non-volatile data
MPU data XRAM
Peripheral control
Note: The IRAM is part of the core and is addressed differently.
Memory Size
(bytes)
64KB
2KB
1KB
Program Memory: The 80515 can address up to 64KB of program memory space from 0x0000 to
0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program
memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting
from 0x0003 (Reset is located at 0x0000).
Flash Memory: The program memory consists of flash memory. The flash memory is intended to
primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to
specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent
inadvertent erasure of the flash memory.
Rev. 1.4
11
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