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PDF 73S8023C Data sheet ( Hoja de datos )

Número de pieza 73S8023C
Descripción Smart Card Interface
Fabricantes Teridian Semiconductor 
Logotipo Teridian Semiconductor Logotipo



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No Preview Available ! 73S8023C Hoja de datos, Descripción, Manual

Simplifying System Integration™
www.DataSheet4U.com
73S8023C
Smart Card Interface
DATA SHEET
April 2009
DESCRIPTION
The Teridian 73S8023C is a low-power, high efficiency,
single smart card interface IC suitable for 3V and 5V
cards. It provides full electrical compliance with ISO-
7816-3 and EMV 4.0 (EMV2000) specifications.
Hardware support for any type of synchronous cards
(memory cards) is provided.
Interfacing with the system controller is done through the
control bus; composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults. Data exchange
with the card is managed from the system controller using
the I/O line (and eventually the auxiliary I/O lines).
A chip select input allows multiple 73S8023C ICs to share
the same control bus. When chip select is set low, the
host microcontroller inputs are latched and outputs are
taken to a high impedance state.
The card clock signal can be generated by an on-chip
oscillator using an external crystal or by connecting an
external clock signal.
The 73S8023C device incorporates an ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Emergency card deactivation is initiated upon
card extraction or upon any fault generated by the
protection circuitry.
The 73S8023C requires only a single 2.7 V to 3.6 V power
supply, and features a high-efficiency embedded DC-DC
converter. This architecture, plus a Power Down digital
input that allow placing the IC in a very low-power mode
making the 73S8023C particularly suitable for low-power
applications (cell-phones, PDAs, payphones, hand-held
POS terminals…).
ADVANTAGES
Supports both synchronous and asynchronous smart
cards
Replacement for TDA8002, with up to 600 mW in
power savings (@ EMV ICCmax condition) !
The inductor-based DC-DC converter provides higher
current and efficiency
Ideal for battery-powered applications
Suitable for high current cards and SAMs: (100 mA
max)
Single 2.7 V to 3.6 V power supply allows removal
of 5 V from the system
Power down mode: 2 µA typical
Package: Small Format (5x5mm) 32-QFN
FEATURES
Card Interface:
Complies with ISO-7816-3, EMV 4.0
A DC-DC Converter provides 3V / 5V to the card
from an external power supply input
High-efficiency converter: > 80% @ VDD=3.3 V,
VCC=5 V and ICC = 65 mA
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation
Protection includes 2 voltage supervisors which
detect voltage drops on card VCC and on VDD
power supply
The VDD voltage supervisor threshold value can be
externally adjusted
True over-current detection (150 mA max.)
2 card detection inputs, 1 for either possible switch
configuration
Full support of synchronous cards
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
3 Digital inputs control the card clock (division rate
and card clock source selection)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults
1 Power down digital input (places the 73S8023C
in a very low-power mode (card deactivated)
1 Chip select digital input for parallel operation of
several 73S8023C ICs.
1 External clock input (STROBE), used for
synchronous operation
1 Digital output clock, buffered version of signal on
XTALIN
Crystal oscillator or host clock (XTALIN), up to
27 MHz
Power Supply: VDD 2.7 V to 3.6 V
6 kV ESD Protection on the card interface
APPLICATIONS
Point of Sales and Transaction Terminals
Payphones
Set-Top-Boxes, DVD / HDD Recorders
Payment card interfaces in portable devices (PDAs,
mobile phones…)
Rev. 1.5
© 2009 Teridian Semiconductor Corporation
1

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73S8023C pdf
DS_8023C_019
73S8023CwwDwa.DtaataSShheeete4Ut .com
1 Pin Description
1.1 Card Interface
Name
I/O
AUX1
AUX2
RST
CLK
PRES
PRES
VCC
GND
Pin Description
9 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
14 Card reset: Provides reset (RST) signal to card.
13 Card clock: Provides clock (CLK) signal to card. The rate of this clock is
determined by crystal oscillator frequency and CLKDIV selections.
7 Card Presence switch: Active high indicates card is present. Includes a
pull-down current source.
6 Card Presence switch: Active low indicates card is present. Includes a pull-up
current source.
15 Card power supply: Logically controlled by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
12 Card ground.
1.2 Miscellaneous Inputs and Outputs
Name
Pin Description
XTALIN
23 Crystal oscillator input: can either be connected to crystal or driven as a
source for the card clock.
XTALOUT
24 Crystal oscillator output: connected to crystal. Left open if XTALIN is being
used as external clock input.
VDDF_ADJ 17 VDD fault threshold adjustment input: this pin can be used to adjust VDDF
value (that controls deactivation of the card). Must be left open if unused.
NC 4 Non-connected pin. Must be left open.
1.3 Power Supply and Ground
Name
VDD
GND
GND
LIN
Pin
3, 20
1
21
2
Description
System controller interface supply voltage: Supply voltage for internal power
supply and DC-DC converter power supply source.
DC-DC converter ground.
Digital ground.
External inductor. Connect external inductor from pin 2 to VDD. Keep the
inductor close to pin 2.
Rev. 1.5
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73S8023C arduino
DS_8023C_019
73S8023CwwDwa.DtaataSShheeete4Ut .com
8 Activation and Deactivation
8.1 Activation Sequence (Synchronous Mode)
The 73S8023C smart card interface IC has an internal ~10 ms delay at power-on reset or on application
of VDD > VDDF. No activation is allowed at this time. CMDVCC (edge triggered) must then be set low to
activate the card.
The following steps list the activation sequence and the timing of the card control signals when the
system controller sets CMDVCC low:
1. CMDVCC is set low.
2. Turn on VCC and I/O (AUX1, AUX2) to reception mode at the end of (tACT).
3. RST is a copy of RSTIN and CLK is a copy of STROBE after (t1).
CMDVCC
VCC
IO
RSTIN
RST
STROBE
CLK
tACT t1
tACT ~= 500µs
t1 > 0.5µs after tACT, RST = RSTIN, CLK = STROBE
Figure 3: Activation Sequence – Synchronous Mode
8.2 Deactivation Sequence (Synchronous Mode)
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, VDD fault and card extraction
during the session and are indicated to the system controller by the fall of OFF.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or a fault condition sets OFF low:
1. RST goes low at time t1.
2. CLK stops low at time t2.
3. I/O goes low at time t3. Out of reception mode.
4. VCC is shut down at time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
Rev. 1.5
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