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PDF 73S8024C Data sheet ( Hoja de datos )

Número de pieza 73S8024C
Descripción Smart Card Interface
Fabricantes Teridian Semiconductor 
Logotipo Teridian Semiconductor Logotipo



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No Preview Available ! 73S8024C Hoja de datos, Descripción, Manual

Simplifying System Integration™
www.DataSheet4U.com
73S8024C
Smart Card Interface
DATA SHEET
April 2009
DESCRIPTION
The Teridian 73S8024C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3, EMV 4.0 and NDS specifications1.
Interfacing with the system controller is done through
the control bus, composed of digital inputs to control
the interface, and one interrupt output to inform the
system controller of the card presence and faults.
Data exchange with the card is managed from the
system controller using the I/O line (and eventually
the auxiliary I/O lines). Hardware support for
auxiliary I/O lines, C4 / C8 contacts, is provided.
The card clock signal can be generated by an on-chip
oscillator using an external crystal or by connection to
a clock signal coming from the system controller.
The Teridian 73S8024C device incorporates an
ISO-7816-3 activation/deactivation sequencer that
controls the card signals. Level shifters drive the
card signals with the selected card voltage (3 V or
5 V), coming from an internal DC-DC converter.
With its high-efficiency DC-DC converter, the
Teridian 73S8024C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a VDD (digital
power supply) or a VCC (card power supply) failure,
a card over-current, or an over-heating fault.
ADVANTAGES
The only smart card interface IC firmware
compatible with the TDA8004 operating with a
single 2.7 V to 3.6 V power supply (allows
removal of 5 V from the system)
The inductor-based DC-DC converter provides
higher current and efficiency than the usual
charge-pump capacitor-based converters
Ideal for battery-powered applications
Suitable for high current cards and SAMs:
(100 mA max)
Power down mode: 2 µA typical
FEATURES
Card Interface:
Complies with ISO-7816-3, EMV 4.0 and NDS1
A DC-DC Converter provides 3V / 5V to the
card from an external power supply input
High-efficiency converter: > 80% @
VDD=3.3 V, VCC=5 V and ICC = 65 mA
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation
sequencer with emergency automated
deactivation on card removal or fault
detected by the protection circuitry
Protection includes 2 voltage supervisors
which detect voltage drops on card VCC and
on VDD power supplies
The VDD voltage supervisor threshold value
can be externally adjusted
True over-current detection (150 mA max.)
2 card detection inputs, 1 for each possible
user polarity
Auxiliary I/O lines, for C4/C8 contact signals
Card clock up to 20 MHz
System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock
(division rate and card clock stop modes)
1 Digital output, interrupt to the system
controller, allows the system controller to
monitor the card presence and faults.
Crystal oscillator or host clock, up to 27 MHz
Power Supply: VDD 2.7 V to 3.6 V
Power Down mode
6 kV ESD Protection on the card interface
Package: SO28
APPLICATIONS
Set-Top-Boxes , DVD / HDD Recorders
Point of Sales and Transaction Terminals
Control Access and Identification
1 Pending NDS approval.
Rev. 1.3
© 2009 Teridian Semiconductor Corporation
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73S8024C pdf
DS_8024C_023
73S8024CwwDwa.DtaataSShheeete4Ut .com
1.4 Microcontroller Interface
Name
CMDVCC
5V/#V
PWRDN
CLKDIV1
CLKDIV2
Pin
(SO)
19
3
8
1
2
Description
Command VCC (negative assertion): Logic low on this pin causes the DC-DC
converter to ramp the VCC supply to the card and initiates a card activation sequence.
5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic
low selects 3 volt operation. When the part is to be used with a single card voltage,
this pin should be tied to either GND or VDD. However, it includes a high impedance
pull-up resistor to default this pin high (selection of 5 V card) when unconnected.
Power Down control input (active high): When Power Down (PD) mode is
activated; all internal analog functions are disabled to place the 73S8024C in its
lowest power consumption mode. The PD mode is allowed only out of a card
session (= PWRDN high is not taken into account when CMDVCC = 0). Must be
tied to ground when the power down function is not used.
Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card
clock. These pins include pull-down resistors.
OFF
RSTIN
I/OUC
AUX1UC
AUX2UC
CLKDIV1 CLKDIV2
Clock Rate
0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
10
XTALIN
23 Interrupt signal to the processor (active low): Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20 kΩ pull-up to VDD.
20 Reset Input: This signal is the reset command to the card.
26 System controller data I/O to/from the card. Includes internal pull-up resistor to VDD.
27 System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to VDD.
28 System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to VDD.
Rev. 1.3
5

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73S8024C arduino
DS_8024C_023
73S8024CwwDwa.DtaataSShheeete4Ut .com
CMDVCC
OFF
-- OR --
RST
CLK
I/O
VCC
t2 t3
t1 t4
t10.5 µs, timing by 1.5 MHz internal Oscillator
t2 7.5 µs t3 0.5 µs t4 0.5 µs
t5 = depends on VCC filter capacitor
For NDS application, CF = 1 µF making t1 + t2 + t3 + t4 + t5 < 100 µs
Figure 5: Deactivation Sequence
t5
10 OFF and Fault Detection
There are two cases for which the system controller can monitor the OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.
Monitoring Outside a Card Session
In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is
present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No
deactivation is required during this time.
Monitoring During a Card Session
CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same
time that OFF is set low, the sequencer starts the deactivation process.
Figure 6 shows the timing diagram for the CMDVCC, PRES, and OFF signals during a card session and
outside the card session.
OFF is low by
card extracted
OFF is low by
any fault
PRES
OFF
CMDVCC
VCC
outside card session
within card session
within card
session
Figure 6: Timing Diagram – Management of the Interrupt Line OFF
Rev. 1.3
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