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PDF MAX11627 Data sheet ( Hoja de datos )

Número de pieza MAX11627
Descripción 300ksps ADCs
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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No Preview Available ! MAX11627 Hoja de datos, Descripción, Manual

19-5323; Rev 0; 6/10
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
General Description
The MAX11626–MAX11629/MAX11632/MAX11633 are
serial 12-bit analog-to-digital converters (ADCs) with an
internal reference. These devices feature on-chip FIFO,
scan mode, internal clock mode, internal averaging,
and AutoShutdown™. The maximum sampling rate is
300ksps using an external clock. The MAX11632/
MAX11633 have 16 input channels; the MAX11628/
MAX11629 have 8 input channels; and the MAX11626/
MAX11627 have 4 input channels. These eight devices
operate from either a +3V supply or a +5V supply, and
contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-com-
patible serial port.
The MAX11626–MAX11629 are available in 16-pin
QSOP packages. The MAX11632/MAX11633 are avail-
able in 24-pin QSOP packages. All eight devices are
specified over the extended -40°C to +85°C tempera-
ture range.
________________________Applications
System Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Instrumentation
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations
TOP VIEW
+
AIN0 1
AIN1 2
AIN2 3
AIN3 4
AIN4 (N.C.) 5
MAX11626–
MAX11629
AIN5 (N.C.) 6
AIN6 (N.C.) 7
AIN7/(CNVST) 8
16 EOC
15 DOUT
14 DIN
13 SCLK
12 CS
11 VDD
10 GND
9 REF
QSOP
() MAX11626/MAX11627 ONLY
Pin Configurations continued at end of data sheet.
Features
o Analog Multiplexer with Track/Hold
16 Channels (MAX11632/MAX11633)
8 Channels (MAX11628/MAX11629)
4 Channels (MAX11626/MAX11627)
o Single Supply
2.7V to 3.6V (MAX11627/MAX11629/MAX11633)
4.75V to 5.25V
(MAX11626/MAX11628/MAX11632)
o Internal Reference
2.048V (MAX11627/MAX11629/MAX11633)
4.096V (MAX11626/MAX11628/MAX11632)
o External Reference: 1V to VDD
o 16-Entry First-In/First-Out (FIFO)
o Scan Mode, Internal Averaging, and Internal Clock
o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing
Codes Over Temperature
o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible
Interface
o Small Packages
16-Pin QSOP (MAX11626–MAX11629)
24-Pin QSOP (MAX11632/MAX11633)
Ordering Information
PART
NUMBER
OF
INPUTS
SUPPLY
VOLTAGE
RANGE (V)
PIN
PACKAGE
MAX11626EEE+* 4 4.75 to 5.25 16 QSOP
MAX11627EEE+*
4
2.7 to 3.6 16 QSOP
MAX11628EEE+* 8 4.75 to 5.25 16 QSOP
MAX11629EEE+*
8
2.7 to 3.6 16 QSOP
MAX11632EEG+
16 4.75 to 5.25 24 QSOP
MAX11633EEG+
16
2.7 to 3.6 24 QSOP
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact for availability.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX11627 pdf
www.DataSheet4U.com
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
TIMING CHARACTERISTICS (Figure 1)
(VDD = +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); VDD = +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), fSAMPLE =
300kHz, fSCLK = 4.8MHz (50% duty cycle), VREF = 2.5V (MAX11627//MAX11629/MAX11633); VREF = 4.096V (MAX11626/
MAX11628/MAX11632), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SCLK Clock Period
Externally clocked conversion
tCP
Data I/O
208
100
ns
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS Low to SCLK Setup
CS High to SCLK Setup
CS High After SCLK Hold
CS Low After SCLK Hold
CNVST Pulse Width Low
tCH
tCL
tDOT
tDOD
tDOE
tDS
tDH
tCSS0
tCSS1
tCSH1
tCSH0
tCSPW
CLOAD = 30pF
CLOAD = 30pF
CLOAD = 30pF
CKSEL = 00
CKSEL = 01
40 ns
40 ns
40 ns
40 ns
40 ns
40 ns
0 ns
40 ns
40 ns
0 ns
0 4 μs
40 ns
1.4 μs
CS or CNVST Rise to EOC
Low (Note 7)
Voltage conversion
Reference power-up
7
μs
65
Note 7: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive.
Typical Operating Characteristics
(VDD = +3V, VREF = +2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C, unless otherwise noted.)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11626/MAX11628/MAX11632
fSAMPLE = 300ksps
1024 2048 3072
OUTPUT CODE (DECIMAL)
4096
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11627/MAX11629/MAX11633
fSAMPLE = 300ksps
1024 2048 3072
OUTPUT CODE (DECIMAL)
4096
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX11626/MAX11628/MAX11632
fSAMPLE = 300ksps
1024 2048 3072
OUTPUT CODE (DECIMAL)
4096
_______________________________________________________________________________________ 5

5 Page





MAX11627 arduino
www.DataSheet4U.com
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
CS
SCLK
DIN
DOUT
tCSS0
tCH
tCL
tDH
tDS
tDOE
tCP
tDOT
tCSH1
tCSH0
tCSS1
tDOD
Figure 1. Detailed Serial-Interface Timing Diagram
CS
DIN
SCLK
SERIAL
INTERFACE
DOUT
CNVST
OSCILLATOR
CONTROL
EOC
AIN1
AIN2
AIN15
REF
T/H
12-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
INTERNAL
REFERENCE
MAX11626–MAX11629/MAX11632/MAX11633
Figure 2. Functional Diagram
Detailed Description
The MAX11626–MAX11629/MAX11632/MAX11633 are
low-power, serial-output, multichannel ADCs with FIFO
capability for system monitoring, process-control, and
instrumentation applications. These 12-bit ADCs have
internal track and hold (T/H) circuitry supporting single-
ended inputs. Data is converted from analog voltage
sources in a variety of channel and data-acquisition con-
figurations. Microprocessor (µP) control is made easy
through a 3-wire SPI-/QSPI-/MICROWIRE-compatible
serial interface.
Figure 2 shows a simplified functional diagram of the
MAX11626–MAX11629/MAX11632/MAX11633 internal
architecture. The MAX11632/MAX11633 have 16 sin-
gle-ended analog input channels. The MAX11628/
MAX11629 have 8 single-ended analog input channels.
The MAX11626/MAX11627 have 4 single-ended analog
input channels.
______________________________________________________________________________________ 11

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