PDF ICS841664I Data sheet ( Hoja de datos )

Número de pieza	ICS841664I
Descripción	FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR
Fabricantes	Integrated Device Technology
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No Preview Available ! www.DataSheet4U.com PRELIMINARY FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR GENERAL DESCRIPTION The ICS841664I is an optimized sRIO clock ICS generator and member of the HiPerClocks™ family HiPerClockS™ of high-perfor mance clock solutions from IDT. The device uses a 25MHz parallel crystal to gen- erate 125MHz and 156.25MHz clock signals, replacing solutions requiring multiple oscillator and fanout buffer solutions. The device has excellent phase jitter (< 1ps rms) suit- able to clock components requiring precise and low-jitter sRIO clock signals. Designed for telecom, networking and industrial applications, the ICS841664I can also drive the high-speed sRIO SerDes clock inputs of communication processors, DSPs, switches and bridges. ICS841664I FEATURES • Four differential HCSL clock outputs: configurable for sRIO (125MHz or 156.25MHz) clock signals One REF_OUT LVCMOS/LVTTL clock output • Selectable crystal oscillator interface, 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended reference clock input • Supports the following output frequencies: 125MHz or 156.25MHz • VCO: 625MHz • PLL bypass and output enable • RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz): 0.35ps (typical) @ 125MHz • Full 3.3V power supply mode • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM XTAL_IN XTAL_OUT OSC REF_IN Pulldown 0 1 REF_SEL Pulldown IREF BYPASS Pulldown FSEL[0:1] Pulldown MR/nOE Pulldown 1 FemtoClock PLL 0 ÷NA VCO = 625MHz M = ÷25 ÷NB nREF_OE Pullup QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 REF_OUT PIN ASSIGNMENT VDD REF_OUT GND QA0 nQA0 VDDOA GND QA1 nQA1 nREF_OE BYPASS REF_IN REF_SEL VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 IREF 27 FSEL0 26 FSEL1 25 QB0 24 nQB0 23 VDDOB 22 GND 21 QB1 20 nQB1 19 MR/nOE 18 VDD 17 XTAL_IN 16 XTAL_OUT 15 GND ICS841664I 28-Lead TSSOP 6.1mm x 9.7mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT™ / ICS™ HCSL CLOCK GENERATOR 1 ICS841664AGI REV. A JANUARY 30, 2009 1 page ICS841664I FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR www.DPatRaSEhLeeItM4UIN.coAmRY TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. Minimum Typical Maximum Fundamental 25 50 7 0.1 Units MHz Ω pF mW TABLE 6A. LVCMOS AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX tR / tF odc Output Frequency REF_OUT Output Rise/Fall Time Output Duty Cycle 20% to 80% Minimum Typical 25 1 50 Maximum Units MHz ns % TABLE 6B. HCSL AC CHARACTERISTICS, V= DD V DDOA =V DDOB = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency VCO/5 VCO/4 125 156.25 MHz MHz tjit(Ø) RMS Phase Jitter (Random); NOTE 1 125MHz, (1.875MHz - 20MHz) 156.25MHz, (1.875MHz - 20MHz) 0.35 ps 0.35 ps tsk(o) Output Skew; NOTE 2, 3 QAx/nQAx, QBx/nQBx ps tL VHIGH VLOW VOVS VUDS Vrb VCROSS ΔVCROSS PLL Lock Time Voltage High Voltage Low Max. Voltage, Overshoot Min. Voltage, Undershoot Ringback Voltage Absolute Crossing Voltage Total Variation of VCROSS over all edges 660 -150 0.3 -0.3 0.2 250 700 1 ms 850 mV 150 mV 0.3 V -0.3 V V 550 mV 140 mV tR / tF Output Rise/Fall Time QAx/nQAx, QBx/nQBx measured between 0.175V to 0.525V 350 ps ΔtR /ΔtF odc Rise/Fall Time Variation Output Duty Cycle QAx/nQAx, QBx/nQBx 125 ps 50 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All specifications are taken at 125MHz and 156.25MHz. NOTE 1: Please refer to the Phase Noise Plot. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ HCSL CLOCK GENERATOR 5 ICS841664AGI REV. A JANUARY 30, 2009 5 Page ICS841664I FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR www.DPatRaSEhLeeItM4UIN.coAmRY SCHEMATIC EXAMPLE Figure 5 shows an example of ICS841664I application schematic. In this example, the device is operated at VCC = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layout, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. One example of HCSL and one example of LVCMOS terminations are shown in this schematic. The decoupling capacitors should be located as close as possible to the power pin. FIGURE 5. ICS841664I SCHEMATIC LAYOUT IDT™ / ICS™ HCSL CLOCK GENERATOR 11 ICS841664AGI REV. A JANUARY 30, 2009 11 Page

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