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PDF FS6377-01g Data sheet ( Hoja de datos )
| Número de pieza | FS6377-01g | |
| Descripción | Programmable 3-PLL Clock Generator IC | |
| Fabricantes | ON Semiconductor | |
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
www.DataSheet4U.com
1.0 Features
• Three on-chip PLLs with programmable reference
and feedback dividers
• Four independently programmable muxes and post
dividers
• I2C™-bus serial interface
• Programmable power-down of all PLLs and output
clock drivers
• One PLL and two mux/post-divider combinations can
be modified by SEL_CD input
• Tristate outputs for board testing
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
• Commercial (FS6377-01) and industrial (FS6377-01i)
temperature ranges
2.0 Description
The FS6377 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of
electronic systems. Three I2C-programmable phase-
locked loops feeding four programmable muxes and post
dividers provide a high degree of flexibility.
SDA 1
SEL_CD 2
PD 3
VSS 4
XIN 5
XOUT 6
OE 7
VDD 8
16 SCL
15 CLK_A
14 VDD
13 CLK_B
12 CLK_C
11 VSS
10 CLK_D
9 ADDR
16-pin (0.150") SOIC
Figure 1: Pin Configuration
XIN
XOUT
PD
SCL
SDA
ADDR
SEL_CD
OE
Reference
Oscillator
Power Down
Control
I2C-bus
Interface
PLL A
PLL B
PLL C
Mux A
Post
Divider A
Mux B
Post
Divider B
Mux C
Post
Divider C
CLK_A
CLK_B
CLK_C
Mux D
Post
Divider D
CLK_D
Figure 2: Block Diagram
FS6377
AMI Semiconductor
www.amis.com
1
1 page  
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
www.DataSheet4U.com
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of
PLL C, muxes C and D and post dividers C and D without
having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a "C1" or "D1"
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with "C2" or "D2" notation, per
Table 3.
Note that changing between two running frequencies us-
ing the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those
portions of the FS6377 which have their respective
powerdown control bits enabled. Note that the PD pin has
an internal pull-up.
When a post divider is powered down, the associated
output driver is forced low. When all PLLs and post
4.3 Oscillator Overdrive
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
should be left unconnected (float).
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
5.0 I2C-bus Control Interface
This device is a read/write slave device
meeting all Philips I2C-bus specifications
except a "general call." The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access and
generates the START and STOP conditions while the
device works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master device
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus
is not busy. During the data transfer, the data line (SDA)
must remain stable whenever the clock line (SCL) is high.
Changes in the data line while the clock line is high will be
dividers are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note
that this pin has an internal pull-up.
rise and fall times and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the refer-
ence must be AC coupled to XOUT through a 0.01mF or
0.1mF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
determines which mode is activated. A device that sends
data onto the bus is defined as the transmitter, and a
device receiving data as the receiver.
I2C-bus logic levels noted herein are based on a
percentage of the power supply (VDD). A logic-one
corresponds to a nominal voltage of VDD, while a logic-zero
corresponds to ground (VSS).
interpreted by the device as a START or STOP condition.
The following bus conditions are defined by the I2C-bus
protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
AMI Semiconductor
www.amis.com
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5 Page 
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
www.DataSheet4U.com
Table 8. PLL Tuning Bits
Name
LFTC_A
(Bit 20)
LFTC_B
(Bit 44)
LFTC_C1
(Bit 68)
LFTC_C2
(Bit 92)
CP_A
(Bit 19)
CP_B
(Bit 43)
CP_C1
(Bit 67)
CP_C2
(Bit 91)
Description
Loop Filter Time Constant A
Bit = 0
Short time constant: 7ms
Bit = 1
Long time constant: 20ms
Loop Filter Time Constant B
Bit = 0
Short time constant: 7ms
Bit = 1
Long time constant: 20ms
Loop Filter Time Constant C1
selected when the SEL_CD pin = 0
Bit = 0
Short time constant: 7ms
Bit = 1
Long time constant: 20ms
Loop Filter Time Constant C2
selected when the SEL_CD pin = 1
Bit = 0
Short time constant: 7ms
Bit = 1
Long time constant: 20ms
Charge Pump A
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
Charge Pump B
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
Charge Pump C1
selected when the SEL_CD pin = 0
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
Charge Pump C2
selected when the SEL_CD pin = 1
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
Table 9. Mux Select Bits
Name
Description
MUX A Frequency Select
Bit 23
Bit 22
MUX_A[1:0]
(Bits 23-22)
0
0
1
0 Reference frequency
1 PLL A frequency
0 PLL B frequency
1 1 PLL C frequency
MUX B Frequency Select
Bit 47
Bit 46
MUX_B[1:0]
(Bits 47-46)
0
0
1
0 Reference frequency
1 PLL A frequency
0 PLL B frequency
1 1 PLL C frequency
MUX C1 Frequency Select
selected when the SEL_CD pin = 0
Bit 71
Bit 70
MUX_C1[1:0]
(Bits 71-70)
0
0
1
0 Reference frequency
1 PLL A frequency
0 PLL B frequency
1 1 PLL C frequency
MUX C2 Frequency Select
selected when the SEL_CD pin = 1
Bit 125 Bit 124
MUX_C2[1:0]
(Bits 125-124)
0
0
1
0 Reference frequency
1 PLL A frequency
0 PLL B frequency
1 1 PLL C frequency
MUX D1 Frequency Select
selected when the SEL_CD pin = 0
Bit 95
Bit 94
MUX_D1[1:0]
(Bits 95-94)
0
0
1
0 Reference frequency
1 PLL A frequency
0 PLL B frequency
1 1 PLL C frequency
MUX D2 Frequency Select
selected when the SEL_CD pin = 1
Bit 127 Bit 126
MUX_D2[1:0]
(Bits 127-126)
0
0
1
0 Reference frequency
1 PLL A frequency
0 PLL B frequency
1 1 PLL C frequency
AMI Semiconductor
www.amis.com
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