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PDF FS6377 Data sheet ( Hoja de datos )
| Número de pieza | FS6377 | |
| Descripción | Programmable 3-PLL Clock Generator IC | |
| Fabricantes | ON Semiconductor | |
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FS6377www.DataSheet4U.com
Programmable 3-PLL Clock Generator IC
1.0 Key Features
• Three on-chip PLLs with programmable reference and feedback dividers
• Four independently programmable muxes and post dividers
• I2C™-bus serial interface
• Programmable power-down of all PLLs and output clock drivers
• One PLL and two mux/post-divider combinations can be modified by SEL_CD input
• Tristate outputs for board testing
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
• Commercial and industrial temperature ranges offered
2.0 General Description
The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three
I2C-programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility.
Figure 1: Pin Configuration
©2008 SCILLC. All rights reserved.
May 2008 – Rev. 4
Publication Order Number:
FS6377/D
1 page  
FS6377
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3.2 Post Divider Muxes
As shown in Figure 2, an input mux in front of each post divider stage can select from any one of the PLL frequencies or the reference
frequency. The frequency selection is done via the I2C-bus.
The input frequency on two of the four muxes (mux C and D in Figure 2) can be changed without reprogramming by a logic-level input
on the SEL_CD pin.
3.3 Post Dividers
The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to
the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
where NF, NR and NP are the feedback, reference and post divider moduli respectively, and fCLK and fREF are the output and reference
oscillator frequencies. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications
where frequencies must be achieved exactly.
The modulus on two of the four post dividers muxes (post dividers C and D in Figure 2) can be altered without reprogramming by a
logic level on the SEL_CD pin.
4.0 Device Operation
The FS6377 powers up with all internal registers cleared to zero, delivering the crystal frequency to all outputs. For operation to occur,
the registers must be loaded in a most significant-bit (MSB) to least-significant-bit (LSB) order. The register mapping of the FS6377 is
shown in Table 3, and I2C-bus programming information is detailed in Section 5.0.
Control of the reference, feedback and post dividers is detailed in Table 5. Selection of these dividers directly controls how fast the VCO
will run. The maximum VCO speed is noted in
Table 13.
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram
the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the
SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-
divider(s) is/are altered.
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective power-down control bits
enabled. Note that the PD pin has an internal pull-up.
When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered down
the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up.
Rev. 4 | Page 5 of 24 | www.onsemi.com
5 Page 
FS6377
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6.2 Power-Down
All power-down functions are controlled by enable bits. The bits select which portions of the device to power-down when the PD input is
asserted.
Table 4: Power-Down Bits
Name
Description
PDPLL_A
(Bit 21)
Power-Down PLL A
Bit = 0
Bit = 1
Power on
Power off
PDLL_B
(Bit 45)
Power-Down PLL B
Bit = 0
Bit = 1
Power on
Power off
Power-Down PLL C
PDLL_C
(Bit 69)
Bit = 0
Bit = 1
Power on
Power off
Reserved
(Bit 69)
(0)
Set these reserved bits to zero (0)
PDPOSTA
(Bit 120)
Power-Down POST Divider A
Bit = 0
Bit = 1
Power on
Power off
PDPOSTB
(Bit 121)
Power-Down POST Divider B
Bit = 0
Bit = 1
Power on
Power off
PDPOSTC
(Bit 122)
Power-Down POST Divider C
Bit = 0
Power on
Bit = 1
Power off
PDPOSTD
(Bit 123)
Power-Down POST Divider D
Bit = 0
Bit = 1
Power on
Power off
Table 5: Divider Control Bits
Name
Description
REFDIV_A[7:0]
(Bits 7-0)
Reference Divider A (NR)
REFDIV_B[7:0]
(Bits 31-24)
REFDIV_C1[7:0]
(Bits 55-48)
REFDIV_C2[7:0]
(Bits 79-72)
Reference Divider B (NR)
Reference Divider C1 (NR)
selected when the SEL_CD pin = 0
Reference Divider C2 (NR)
selected when the SEL_CD pin = 1
FBKDIV_A[10:0]
(Bits 18-8)
Feedback Divider A (NF)
FBKDIV_A[2:0]
A-Counter value
FBKDIV_A[10:3]
M-Counter value
FBKDIV_B[10:0]
(Bits 42-32)
Feedback Divider B (NF)
FBKDIV_B[2:0]
A-Counter value
FBKDIV_B[10:3]
M-Counter value
Feedback Divider C1 (NF)
selected when the SEL_CD pin = 0
FBKDIV_C1[10:0] FBKDIV_C1[2:0]
A-Counter value
(Bits 66-56)
FBKDIV_C1[10:3] M-Counter value
Feedback Divider C2 (NF)
selected when the SEL_CD pin = 1
FBKDIV_C2[10:0] FBKDIV_C2[2:0] A-Counter value
(Bits 90-80)
FBKDIV_C2[10:3] M-Counter value
Rev. 4 | Page 11 of 24 | www.onsemi.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet FS6377.PDF ] | |
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