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PDF TFF11084HN Data sheet ( Hoja de datos )
| Número de pieza | TFF11084HN | |
| Descripción | Low Phase Noise LO Generator | |
| Fabricantes | NXP Semiconductors | |
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TFF11084HN
Low phase noise LO generator for VSAT applications
Rev. 1 — 12 July 2010
Objective data sheet
1. General description
The TFF11084HN is a Ku band frequency generator intended for low phase noise Local
Oscillator (LO) circuits for Ku band VSAT transmitters and transceivers. The specified
phase noise complies with IESS-308 from Intelsat.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
2. Features and benefits
Phase noise compliant with IESS-308 (Intelsat) in combination with appropriate source
LO generator with VCO range from 8.20 GHz to 8.60 GHz
Input signal 32 MHz to 538 MHz
Divider settings 16, 32, 64, 128 or 256
Output level −5 dBm; stability ±2 dB
Third or fourth order PLL
Internally stabilized voltage references for loop filter
3. Applications
VSAT up converters
Local oscillator signal generation
4. Quick reference data
Table 1. Quick reference data
Operating conditions of Table 10 apply.
Symbol Parameter
VCC
ICC
fo(RF)
ϕn(synth)
supply voltage
supply current
RF output frequency
synthesizer phase noise
RLout
output return loss
αsup(sp)ref reference spurious suppression
Conditions
divider value = 64; at 100 kHz offset; reference
phase noise is −149 dBc/Hz at 100 kHz offset
measured at demo board and de-embedded to
footprint
measured at divider value = 256
Min Typ Max
3.0 3.3 3.6
- 100 130
8.20 - 8.60
- −97 −92
Unit
V
mA
GHz
dBc/Hz
- −10 -
dB
- - −70 dBc
1 page  
NXP Semiconductors
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TFF11084HN
Low phase noise LO generator for VSAT applications
Table 4. Pin description …continued
Symbol
Pin Description
VCC(BUF)
18 Supply voltage for the RF output buffer. Decouple this pin against GND2(BUF)
(pin 19).
GND2(BUF) 19 Ground for RF output. Connect this pin to the exposed diepad landing.
BUF1_N 20 RF output.
BUF2_N 21 RF output.
BUF1_P 22 RF output.
BUF2_P 23 RF output.
GND3(BUF) 24 Ground for RF output. Connect this pin to the exposed diepad landing.
10. Functional description
The TFF11084HN consists of the following blocks:
• PLL
• Output buffer
• Lock detector
• Reference input
• Divider settings
The functionality of the blocks will be discussed below.
10.1 PLL
The PLL is formed by the VCO, DIVIDER (possible settings: 16, 32, 64, 128 and 256
(see Table 8)) and a PFD/CP. The tune voltage is referred to the band gap regulated
voltage: VREGVCO (pin 1).
The loop filter can be set to type 2 or type 3. If a type 2 filter is used, the pins
CPOUT (pin 2) and VTUNE (pin 3) must be interconnected. A 10 pF capacitor is placed
internally between pins CPOUT (pin 2) and VREGVCO (pin 1), and a 30 pF capacitor is
placed between pins VTUNE (pin 3) and VREGVCO (pin 1). See Figure 4 and Figure 5.
Values for the loop filter components are given in Table 5.
The VCO input voltage range is between 0.1 and 0.9 VO(reg)VCO.
TFF11084HN
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 July 2010
© NXP B.V. 2010. All rights reserved.
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GND = 0
open or 3.3 V = 1
C2
C1 R1
R2
C3
1 nF
50 Ω
50 Ω
REFERENCE
SOURCE
NSL2
6
100 kΩ
pull up
NSL1
5
100 kΩ
pull up
OUT-OF-LOCK
PROCESSING
BLOCK
lock: 2.5 V
LCKDET 7 no lock: 0 V
100 kΩ
pull down
GND1(REF) 8
WINDOW
DETECTOR
NSL0
4
VTUNE
3
100 kΩ
pull up
VCC(DIV)
(3.3 V)
30 pF
CPOUT
2
10 pF
VREGVCO
1
2.7 V
VCC(BUF)
Z0(dif) = 100 Ω
10 nF IN(REF)_P 9
100 Ω DC block
10 nF IN(REF)_N 10
GND2(REF) 11
CPOUT
PFD CP
DIVIDER
NSL0
NSL1
NSL2
VCO
VTUNE
RBUF_N
50 Ω
RBUF_P
50 Ω
24 GND3(BUF)
23 BUF2_P
1 pF Z0 = 50 Ω
22 BUF1_P
DC block
21 BUF2_N
1 pF Z0 = 50 Ω
20 BUF1_N
3.3 V
VCC(REF) 12
19 GND2(BUF)
50 Ω
50 Ω
LOAD
50 Ω
50 Ω
LOAD
13 14 15 16 17
18
VCC(DIV) GND(DIV) n.c. n.c. GND1(BUF) VCC(BUF)
Fig 7. Application diagram with differential source for IN(REF) and both outputs driving a load, loop filter is type 3
001aal730
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